Embeded DRAM cell structures with high conductance electrodes and methods of manufacture

• US 8,703,572 B2
• Filed: 10/10/2011
• Issued: 04/22/2014
• Est. Priority Date: 10/10/2011
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Williams, Richard Q.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): NGUYEN, DUY T V
• Application Number:
  US13/269,955
• Publication Number:
  US 20130087841A1
• Time in Patent Office: 925 Days
• Field of Search: 257/303, 257/E21.645, 438/396, 438/367
• US Class Current: 438/367
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.

Claims

1. A method comprising:

forming upper layers on a semiconductor substrate, the semiconductor substrate being a single uniformly doped layer of silicon substrate;

forming an opening in the upper layers;

forming a trench in the semiconductor substrate, aligned with the opening;

forming a metal plate on all exposed surfaces in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate;

forming an insulator material on the metal plate;

forming an inner plate on the insulator material; and

forming a contact in an oxide layer formed on the inner plate, the contact being formed on a portion of a surface area of the inner plate,

wherein the semiconductor substrate is an electrode that receives the electrical bias.

2. The method of claim 1, wherein the metallic aqueous solution is PtCl₄ or H₂PtCl₆ and the metal plate is a conformal platinum layer on a surface of the trench.

3. The method of claim 2, wherein the conformal platinum layer is about 2-3 nm thick.

4. The method of claim 2,

wherein the metal plate is an outer metal plate formed on exposed surfaces of the trench.

5. The method of claim 1, wherein the metal plate is gold, palladium, platinum, or silver.

6. The method of claim 1, further comprising forming a diffusion region in the semiconductor substrate of the trench, wherein the metal plate is provided on the diffusion region and completely fills the trench and the opening.

7. The method of claim 1, further comprising protecting sidewalls of the opening with a mask material, prior to forming the trench.

8. A method comprising:

depositing a pad layer on top of a semiconductor layer provided on an insulator layer and semiconductor substrate, the semiconductor substrate being a single uniformly doped layer of silicon substrate;

depositing a hardmask over the pad layer;

etching an opening through the insulator layer, semiconductor layer, pad layer and hardmask;

forming an isolation spacer along sidewalls of the opening;

etching a trench in the semiconductor substrate and in alignment with the opening;

applying an aqueous solution and electrical bias from a backside of the semiconductor substrate to form a metal plate in the trench;

depositing a dielectric liner on the metal plate;

depositing a polysilicon material in the trench to form an electrode;

forming a contact on a portion of a surface area of the electrode; and

forming an oxide cap layer in the opening, wherein the contact is in the oxide cap layer, and

wherein the semiconductor substrate is configured as another electrode to receive the electrical bias.

9. The method of claim 8, further comprising forming a diffusion region in the semiconductor substrate of the trench, wherein the metal plate is formed on the diffusion region and completely fills the trench and the opening.