Method for fabrication of a semiconductor device and structure

• US 8,703,597 B1
• Filed: 04/25/2013
• Issued: 04/22/2014
• Est. Priority Date: 09/30/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Choi, Calvin
• Application Number:
  US13/869,963
• Time in Patent Office: 362 Days
• Field of Search: None
• US Class Current: 438/599
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/082 including bipolar components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.

Claims

1. A method for fabricating a device, the method comprising:

providing a first layer comprising first transistors,

wherein said first transistors comprise a mono-crystalline semiconductor;

processing a metal layer overlaying said first layer,

wherein said metal layer comprises copper or aluminum;

processing a second layer to overlay said metal layer,

wherein said second layer comprises second transistors,

wherein said second transistors comprise a mono-crystalline semiconductor,

wherein said second layer thickness is less than 200 nm;

fabricating an isolation layer directly overlaying and in contact with said second layer; and

fabricating a third layer directly overlaying and in contact with said isolation layer,

wherein said third layer comprises third transistors,

wherein said third transistors comprise a mono-crystalline semiconductor,

wherein said second transistors and said third transistors are configured to be memory cells, and

wherein said second layer comprises at least one memory cell control line.

2. The method according to claim 1, wherein said second layer has been transferred using an ion-cut layer transfer process.

3. The method according to claim 1, wherein said second transistors are horizontally oriented transistors.

4. The method according to claim 1, wherein said second transistors are aligned to said first transistors.

5. The method according to claim 1, wherein at least one of said memory cells comprise a floating body type memory cell.

6. The method according to claim 1, wherein at least one of said memory cells comprise a non-volatile charge-trap region, said non-volatile charge-trap region configured to be charged to a level indicative of a state of the memory cell.

7. A method for fabricating a device, the method comprising:

providing a first layer comprising first transistors,

wherein said first transistors comprise a mono-crystalline semiconductor;

processing a metal layer overlaying said first layer,

wherein said metal layer comprises copper or aluminum;

processing a second layer to overlay said metal layer,

wherein said second layer comprises second transistors,

wherein said second transistors comprise a mono-crystalline semiconductor,

wherein said second layer thickness is less than 200 nm;

fabricating an isolation layer directly overlaying and in contact with said second layer; and

fabricating a third layer directly overlaying and in contact with said isolation layer,

wherein said third layer comprises third transistors,

wherein said third transistors comprise a mono-crystalline semiconductor, and

wherein said second transistors and said third transistors are configured to be memory cells.

8. The method according to claim 7, wherein at least one of said memory cells comprise a non-volatile charge-trap region, said non-volatile charge-trap region configured to be charged to a level indicative of a state of the memory cell.

9. The method according to claim 7, wherein at least one of said memory cells comprise a floating body region, said floating body region configured to be charged to a level indicative of a state of the memory cell.

10. The method according to claim 7, wherein at least one of said memory cells comprise a non-volatile memory cell.

11. The method according to claim 7, further comprising:

fabricating a plurality of memory cell control lines wherein said control lines comprise a portion of said second layer.

12. The method according to claim 7, wherein said second transistors are aligned to said first transistors.

13. A method for fabricating a device, the method comprising:

providing a first layer comprising first transistors,

wherein said first transistors comprise a mono-crystalline semiconductor;

processing a metal layer overlaying said first layer,

wherein said metal layer comprises copper or aluminum;

processing a second layer to overlay said metal layer,

wherein said second layer comprises second transistors,

wherein said second transistors comprise a mono-crystalline semiconductor,

wherein said second layer thickness is less than 200 nm;

fabricating an isolation layer directly overlaying and in contact with said second layer; and

fabricating a third layer directly overlaying and in contact with said isolation layer,

wherein said third layer comprises third transistors,

wherein said third transistors comprise a mono-crystalline semiconductor,

wherein said second transistors and said third transistors are configured to be memory cells,

wherein said device comprises at least three independent control lines, and

wherein each of said three independent control lines is connected directly to at least one of said first transistors.

14. The method according to claim 13, wherein said second layer has been transferred using an ion-cut layer transfer process.

15. The method according to claim 13, wherein said second transistors are horizontally oriented transistors.

16. The method according to claim 13, wherein said second transistors are aligned to said first transistors.

17. The method according to claim 13, wherein one or more of said second transistors form a memory cell of at least one of the following types:

i. a Floating Body memory cell;

ii. an R-RAM memory cell;

or

iii. an M-RAM memory cell.

18. The method according to claim 13, wherein said second transistors overlay said first transistors.

19. The method according to claim 13, wherein at least one of said three independent control lines comprises said first layer.

20. The method according to claim 13, wherein said first layer is overlaying at least one metal layer.