High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability

• US 8,703,605 B2
• Filed: 07/07/2010
• Issued: 04/22/2014
• Est. Priority Date: 12/18/2007
• Status: Expired due to Fees

• Current Assignee: Byung Chun Yang
• Original Assignee: Byung Chun Yang
• Inventors: Yang, Byung Chun
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US12/831,482
• Publication Number:
  US 20100301491A1
• Time in Patent Office: 1,385 Days
• Field of Search: 438/633, 438637-639, 438/706, 438/710, 438/745, 438/906, 257/E21.579, 257/E21.224, 257/E21.226, 257/E21.228, 257/E21.229
• US Class Current: 438/639
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires

Abstract

A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated. By performing further damascene process steps over already formed damascene interconnect features, various interconnect systems, such as a single damascene planar via, a single damascene embedded via and a dual damascene interconnect system having either a planar via or an embedded via, can be fabricated. Dual damascene interconnect structures having either a sacrificial layer incorporated in them or having no sacrificial layer incorporated in them are also provided.

Claims

1. A method for fabricating an interconnect system, comprising:

a. depositing a dielectric layer over a substrate, said substrate having formed therein a conductor of a selected thickness;

b. etching a preliminary contact opening in said dielectric layer over said conductor;

c. depositing a sacrificial layer over the surface of a sidewall of said preliminary contact opening;

d. with said sacrificial layer protecting said sidewall of said preliminary contact opening, forming a recess in said conductor at the bottom of said preliminary contact opening by performing an etch back process; and

e. performing a residue removal process to remove at least a portion of said sacrificial layer and residue resulting from said etch back process to form a final contact opening.

2. The method of claim 1, wherein said dielectric layer comprises a composite of multiple dielectric layers.

3. The method of claim 2, wherein said composite of multiple dielectric layers comprises one or more interlevel dielectric (ILD) layers and one or more other dielectric layers than said interlevel dielectric layers.

4. The method of claim 3, wherein said one or more other dielectric layers are each selected from a group consisting of a capping layer, a dielectric diffusion barrier layer, a passivation layer, and a chemical mechanical polishing (CMP) stop layer.

5. The method of claim 1, wherein said etching a preliminary contact opening is performed by a plasma etch process using one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

6. The method of claim 1, wherein said etching a preliminary contact opening stops before said conductor is exposed, thereby a portion of said dielectric layer is retained over said conductor at the bottom of said preliminary contact opening.

7. The method of claim 1, wherein said etching a preliminary contact opening is continued until said dielectric layer deposited over said conductor is etched through at the bottom of said preliminary contact opening.

8. The method of claim 1, wherein said sacrificial layer is a solid material layer at room temperatures.

9. The method of claim 8, wherein said sacrificial layer comprises one or more elements selected from a group consisting of silicon, oxygen, carbon, nitrogen, hydrogen, fluorine, chlorine, bromine, iodine, boron, phosphor, germanium, and arsenic.

10. The method of claim 8, wherein said sacrificial layer comprises either a single material layer of constant characteristics, a material layer of gradually changing characteristics in its growth direction, or multiple material layers of varying characteristics, each of said characteristics being selected from a group consisting of crystallographic structure, microstructure, conformality, composition, and material property.

11. The method of claim 1, wherein said sacrificial layer is deposited using one or more methods selected from a group consisting of physical vapor deposition methods, chemical deposition methods, spray pyrolysis methods, electrochemical deposition methods, electroless deposition methods, and spin on methods.

12. The method of claim 1, wherein said sacrificial layer is deposited using one or more chemical deposition methods.

13. The method of claim 1, further comprising, performing an additional etch back process for adjusting the conformality of said sacrificial layer prior to said forming a recess.

14. The method of claim 1, further comprising, pretreating said dielectric layer prior to said depositing a sacrificial layer using one or more dielectric layer pretreatment processes selected from a group consisting of wet clean processes, degas processes, plasma clean processes, densification processes, and silylation processes.

15. The method of claim 1, wherein said etch back process is performed by using one or more plasma processes each of which uses one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

16. The method of claim 1, wherein said etch back process is performed using a sputter etch in a plasma of one or more inert gases selected from a group consisting of He, Ar, Xe, Kr and Ne.

17. The method of claim 1, wherein said etch back process is continued after the materials existing over said conductor at the bottom of said preliminary contact opening is removed, thereby forming said recess in said conductor.

18. The method of claim 17, wherein the depth of said recess ranges from one atomic monolayer of said conductor to said selected thickness.

19. The method of claim 17, wherein the depth of said recess ranges from 5 percent to 50 percent of said selected thickness.

20. The method of claim 1, wherein said residue removal process is carried out by performing a wet clean process or a plasma clean process, or both.

21. The method of claim 20, wherein said wet clean process uses one or more chemicals selected from a group consisting of B₂O₃, Br₂, CH₃COOH, Ce(SO4)2, Ce(SO3)3, CrO₃, CsOH, Cu(NO₃)₂, FeSO₄, FeCl₃, Fe(NO₃)₃, H₂O, H₂O₂, H₂N₄, H₂SO₄, H₃PO₄, HNO₃, HF, H₂S, HCl, HClO₄, HI, HBr, I₂, KI, KOH, KH₂PO₄, KMnO₄, KNO₃, K₂Fe(CN)₆, K₂Cr₂O₇, K₃Fe(CN)₆, K₄Fe(CN)₆, NaOH, NaOCl, Na₂HPO₄, Na₂O, Na₂O₂, NaNO₂, NH₃, NH₄F, NH₄OH, NH₂(CH₂)NH₂, N₂H₈C₂, NHF, N₂H₄, (NH₄)₂S₂O₄, O₃, vinylacetate, dipropyleneglycolmonomethyletheracetate, ethylenediamine, ethylenedibromide, ammoniumcitrate, tetramethylammoniumhydroxide, glycerol, ethyleneglycol, oxalic acid dihydrate, anhydrous oxalic acid, citric acid, benzotriazole, propanol, pyrocatechol, polypropyleneglycol, parabenzoquinon, tartaric acid, ethanol, methanol, and isopropanol.

22. The method of claim 20, wherein said plasma clean process uses one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

23. The method of claim 1, wherein said sacrificial layer is deposited over a preliminary contact opening having a post etch residue remaining thereon.

24. The method of claim 1, further comprising, forming a preliminary trench over said preliminary contact opening before said depositing a sacrificial layer.

25. The method of claim 1, further comprising,

a. depositing a conductive liner layer over the surface of said final contact opening and the surface of said conductor in said recess;

b. filling said final contact opening and said recess that are lined with said conductive liner layer with an upper level conductor; and

c. planarizing said upper level conductor, thereby forming a single damascene contact.

26. The method of claim 25, wherein said upper level conductor comprises one or more conductor materials selected from a group consisting of carbon, pure metal materials, metal alloys, metal silicides, metal oxides, metal nitrides, metal carbides, metal borides, metal carbonitrides, and doped silicons.

57. The method of claim 1, wherein said etching a preliminary contact opening is performed by a wet etch process.

59. The method of claim 1, wherein the diameter of said preliminary contact opening is larger than a target contact diameter of said interconnect system.

27. A method for fabricating a dual damascene interconnect system, comprising:

a. depositing a dielectric layer over a substrate having formed therein a lower level conductor of a selected thickness;

b. etching a preliminary dual damascene feature in said dielectric layer, said preliminary dual damascene feature comprising a preliminary trench and a preliminary via hole, said preliminary via hole underlying said preliminary trench;

c. depositing a sacrificial layer over the surface of a side wall of said preliminary dual damascene feature;

d. with said sacrificial layer protecting said sidewall of said preliminary contact opening, forming a recess in said lower level conductor at the bottom of said preliminary via hole by performing an etch back process; and

e. performing a residue removal process to remove at least a portion of said sacrificial layer and residue resulting from said etch back process, so as to form a final dual damascene feature comprising a final trench and a final via hole.

28. The method of claim 27, wherein said dielectric layer comprises a composite of multiple dielectric layers.

29. The method of claim 28, wherein said composite of multiple dielectric layers comprises one or more interlevel dielectric (ILD) layers and one or more other dielectric layers than said interlevel dielectric layers.

30. The method of claim 29, wherein said one or more other dielectric layers are each selected from a group consisting of capping layers, dielectric diffusion barrier layers, passivation layers, chemical mechanical polishing (CMP) stop layers, and etch stop layers.

31. The method of claim 27, wherein said etching a preliminary dual damascene feature is performed by one or more plasma etch processes using one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

32. The method of claim 27, wherein said etching a preliminary dual damascene feature stops before said dielectric layer deposited over said lower level conductor is etched through at the bottom of said preliminary via hole.

33. The method of claim 27, wherein said etching a preliminary dual damascene feature is continued until said dielectric layer deposited over said lower level conductor is etched through at the bottom of said preliminary via hole.

34. The method of claim 27, wherein said sacrificial layer is a solid material layer at room temperatures.

35. The method of claim 27, wherein said sacrificial layer comprises one or more elements selected from a group consisting of silicon, oxygen, carbon, nitrogen, hydrogen, fluorine, chlorine, bromine, iodine, boron, phosphor, germanium and arsenic.

36. The method of claim 27, wherein said sacrificial layer comprises either a single material layer of constant characteristics, a material layer of gradually changing characteristics in its growth direction, or multiple material layers of varying characteristics, each of said characteristics being selected from a group consisting of crystallographic structure, microstructure, conformality, composition, and material property.

37. The method of claim 27, wherein said sacrificial layer is deposited by one or more methods selected from a group consisting of physical vapor deposition methods, chemical deposition methods, spray pyrolysis methods, electrochemical deposition methods, electroless deposition methods, and spin on methods.

38. The method of claim 27, further comprising, performing an additional etch back process for adjusting the conformality of said sacrificial layer prior to said forming a recess, said additional etch back process being performed in addition to said forming a recess in said lower level conductor.

39. The method of claim 27, further comprising, pretreating said dielectric layer prior to said depositing a sacrificial layer with one or more dielectric layer pretreatment processes selected from a group consisting of wet clean processes, degas processes, plasma clean processes, densification processes, and silylation processes.

40. The method of claim 27, wherein said etch back process is performed by using a plasma process which uses one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

41. The method of claim 27, wherein said etch back process is performed by a sputter etch in a plasma of one or more inert gases selected from a group consisting of He, Ar, Xe, Kr and Ne.

42. The method of claim 27, wherein said etch back process removes materials existing over said lower level conductor at the bottom of said preliminary via hole and a portion of said lower level conductor, thereby forming said recess in said lower level conductor underneath the bottom of said preliminary via hole.

43. The method of claim 42, wherein the depth of said recess formed in said lower level conductor underneath the bottom of said preliminary via hole ranges from one atomic monolayer of said lower level conductor material to said selected thickness.

44. The method of claim 42, wherein the depth of said recess ranges from 5 percent to 50 percent of said selected thickness.

45. The method of claim 32, wherein said residue removal process is carried out by performing a wet clean process or a plasma clean process, or both.

46. The method of claim 45, wherein said wet clean process uses one or more chemicals selected from a group consisting of B₂O₃, Br₂, CH₃COOH, Ce(SO₄)₂, Ce(SO₃)₃, CrO₃, CsOH, Cu(NO₃)₂, FeSO₄, FeCl₃, Fe(NO₃)₃, H₂O, H₂O₂, H₂N₄, H₂SO₄, H₃PO₄, HNO₃, HF, H₂S, HCl, HClO₄, HI, HBr, I₂, KI, KOH, KH₂PO₄, KMnO₄, KNO₃, K₂Fe(CN)₆, K₂Cr₂O₇, K₃Fe(CN)₆, K₄Fe(CN)₆, NaOH, NaOCl, Na₂HPO₄, Na₂O, Na₂O₂, NaNO₂, NH₃, NH₄F, NH₄OH, NH₂(CH₂)NH₂, N₂H₈C₂, NHF, N₂H₄, (NH₄)₂S₂O₄, O₃, vinylacetate, dipropyleneglycolmonomethyletheracetate, ethylenediamine, ethylenedibromide, ammoniumcitrate, tetramethylammoniumhydroxide, glycerol, ethyleneglycol, oxalic acid dihydrate, anhydrous oxalic acid, citric acid, benzotriazole, propanol, pyrocatechol, polypropyleneglycol, parabenzoquinon, tartaric acid, ethanol, methanol, and isopropanol.

47. The method of claim 45, wherein said plasma clean process uses one or more gases selected from a group consisting of He, Ar, Xe, Kr, Ne, atomic hydrogen, atomic hydrogen, H₂, atomic nitrogen, N₂, nitrogen containing compound gases, CO, CO₂, atomic oxygen, O₂, O₃, H₂O, hydrocarbon gases, and a major etchant gas group consisting of halogen gases, halogen containing compound gases that do not contain a sulfur atom, non-sulfide gases containing a sulfur atom, and sulfide gases.

48. The method of claim 27, wherein said sacrificial layer is deposited on the surface of a preliminary dual damascene feature having a post etch residue remaining thereon.

49. The method of claim 27, further comprising,

a. depositing one or more conductive liner layers over said final dual damascene feature and the surface of said conductor in said recess;

b. filling said final dual damascene feature and said recess with an upper level conductor; and

c. planarizing the top surface of said upper level conductor.

50. The method of claim 49, wherein said each of said one or more conductive liner layers comprises either a conductive diffusion barrier layer or an adhesion layer, or both.

51. The method of claim 50, wherein said conductive diffusion barrier layer is deposited by a plasma enhanced chemical deposition method.

52. The method of claim 49, further comprising, performing one or more liner etch back processes prior to filling said final dual damascene feature with an upper level conductor such that the conformality of said conductive liner layers is adjusted at least one time prior to filling said final dual damascene feature with an upper level conductor.

53. The method of claim 49, wherein said filling said final dual damascene feature with an upper level conductor is performed by depositing a copper seed layer, followed by an electrochemical deposition of copper.

54. The method of claim 53, wherein said depositing a copper seed layer is performed by using one or more methods selected from a group consisting of chemical deposition methods, physical vapor deposition methods and electrochemical deposition methods.

55. The method of claim 49, wherein said upper level conductor comprises one or more conductor materials selected from a group consisting of carbon, pure metal materials, metal alloys, metal silicides, metal oxides, metal nitrides, metal carbides, metal borides, metal carbonitrides, and doped silicons.

56. The method of claim 49, wherein said planarizing the top surface of said upper level conductor is performed by a chemical mechanical polishing method.

58. The method of claim 27, wherein said etching a preliminary dual damascene feature is performed by a wet etch process.

60. The method of claim 27, wherein the diameter of said preliminary via hole and the width of said preliminary trench are larger than a target via diameter and a target width of the upper level conductor line of said dual damascene interconnect system, respectively.

61. A method for fabricating an integrated circuit device, comprising:

(a) depositing a sacrificial layer over the surface of a sidewall of a preliminary damascene feature comprising at least a preliminary contact hole, said preliminary damascene feature being formed in a dielectric layer deposited over a substrate, said substrate having a conductor formed therein;

(b) forming a recess in said conductor at the bottom of said preliminary contact hole;

said sacrificial layer protecting said preliminary damascene feature from damage or contamination caused by said forming a recess in said conductor, said forming a recess in said conductor leaving a residue; and

(c) performing a residue removal process, said residue removal process removing at least a portion of said sacrificial layer from said preliminary damascene feature and said residue, said residue removal process forming a final damascene feature comprising at least a final contact hole.