Through-substrate via for semiconductor device

• US 8,703,609 B2
• Filed: 07/01/2011
• Issued: 04/22/2014
• Est. Priority Date: 08/24/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Chen-Cheng, Chen-Shien, Chen, Ching, Kai-Ming, Chen, Chih-Hua
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US13/175,022
• Publication Number:
  US 20110263120A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257/758, 257/E21.575, 257/E21.585, 257/E21.597, 438/589, 438/637, 438/640, 438/667, 438/701
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate having a front surface and an opposing back surface, and wherein the substrate has an interconnect structure formed on the front surface of the substrate, and wherein the interconnect structure has a first surface opposite the front surface of the substrate, and wherein the interconnect structure includes a first conductive layer, a second conductive layer overlying the first conductive layer, and an isolation layer interposing the first conductive layer and the second conductive layer;

depositing a hard mask layer on the interconnect structure;

forming a first opening in the hard mask layer;

depositing a layer of photoresist on the hard mask layer;

forming a second opening in the photoresist, wherein the second opening is aligned with the first opening and has a greater width than the first opening; and

etching a tapered profile via in the substrate aligned with the first and the second openings, wherein the tapered profile via extends from the hard mask layer to the back surface of the semiconductor substrate, wherein a width of the tapered profile via is defined by at least one of the first opening and the second opening.

2. The method of claim 1, further comprising:

depositing an insulating material layer, wherein the deposited insulating material layer is on the hard mask layer and underlying the photoresist.

3. The method of claim 1, wherein the etching the tapered profile includes removing the hard mask layer that does not underlie the deposited photoresist layer.

4. The method of claim 1, wherein the forming the second opening includes forming a tapered edge opening.

5. The method of claim 4, wherein the forming the tapered edge opening includes heating the photoresist to greater than approximately 100 degrees Celsius.

6. The method of claim 4, wherein the forming the tapered edge opening includes performing photolithography process that defines the tapered edge using sub-resolution features of a photomask.

7. The method of claim 1, further comprising:

depositing at least one insulating material layer in the tapered profile via, and

depositing at least one conductive material layer on the at least one insulating material layer.

8. The method of claim 1, further comprising:

depositing an insulating material layer, wherein the deposited insulating material layer is on the hard mask layer and underlying the photoresist; and

etching back the insulating layer to form a third opening in a region overlying the tapered profile via, wherein the third opening has a greater width than the second and first opening.

9. A method of manufacturing a semiconductor device, comprising:

forming a first layer of material including a first opening having a first width on a substrate;

after forming the first layer of material including the first opening, forming a photoresist layer on the first layer of material;

performing a heat treatment on the photoresist layer to form a second opening, wherein the second opening has a second width at an interface between the first opening and the second opening; and

etching a tapered profile via in the substrate underlying the first and second openings using the first layer and the photoresist layer as masking elements, wherein the second width of the second opening is approximately equal to a third width of the tapered profile via and wherein the first width of the first opening is approximately equal to a fourth width of the tapered profile via.

10. The method of claim 9, wherein the performing the heat treatment includes forming a fifth width of the second opening, wherein the fifth width is greater than the second width.

11. The method of claim 9, wherein the heat treatment is performed at greater than 100C.