Semiconductor device

• US 8,704,223 B2
• Filed: 01/08/2008
• Issued: 04/22/2014
• Est. Priority Date: 01/12/2007
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Inventors: Yamagami, Minoru, Nagamine, Hisayuki
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US12/007,220
• Publication Number:
  US 20080169467A1
• Time in Patent Office: 2,296 Days
• Field of Search: 257/48, 257/170, 257/354, 257/401, 257/409, 324/765, 324/158.1, 324/769
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.

Claims

1. A semiconductor device comprising:

a semiconductor circuit region;

a dicing line area formed along said semiconductor circuit region to define the semiconductor circuit region;

at least one characteristic checking element formed in said dicing line area;

a plurality of first pads formed in said dicing line area and electrically connected to said characteristic checking element; and

at least one second pad formed in said semiconductor circuit region apart from said dicing line area and electrically connected to the characteristic checking element, wherein said at least one characteristic checking element is configured to be rendered inoperative by application of a sufficient electric voltage to said second pad during a semiconductor device test operation.

2. The semiconductor device as claimed in claim 1, wherein the semiconductor circuit region includes a sub-connection wiring area formed along a periphery of the semiconductor circuit region and said second pad is connected to said characteristic checking element through a wiring crossing the sub-connection wiring area.

3. The semiconductor device as claimed in claim 1, wherein said characteristic checking element comprises a checking transistor having a drain, a source and a gate each connected to corresponding one of said first pads, the gate being further connected to said second pad.

4. The semiconductor device as claimed in claim 1, wherein said characteristic checking element comprises a plurality of checking transistors each having a drain, a source and a gate, the drains of the checking transistors being connected respectively to different first ones of the first pads, the source of the checking transistors being connected in common to a second one of the first pads, the gates of the checking transistors being connected respectively to third pad of the first pads and further to the second pad.

5. The semiconductor device as claimed in claim 1, wherein said characteristic checking element comprises a checking resistance element and a transistor, the checking resistance element having first and second ends connected respectively to two of the first pads, the transistor having one of drain and source connected to the checking resistance element and a gate connected to the second pad.

6. The semiconductor device as claimed in claim 5, wherein said transistor has the other of the drain and source connected to a substrate of the semiconductor device.

7. The semiconductor device as claimed in claim 1, wherein said characteristic checking element comprising a checking resistance element having first and second ends and a transistor having a gate and first and second diffusion layers, the first and second ends of the checking resistance element being connected respectively to two of said first pads, the gate of the transistor being connected to said second pad, and the first diffusion layer of the transistor being connected to said checking resistance element.

8. The semiconductor device as claimed in claim 7, wherein the second diffusion layer of said transistor being supplied with a substrate potential that is used for the semiconductor circuit region.

9. The device as claimed in claim 1, further comprising a plurality of third pads formed in the semiconductor circuit region along the dicing line area and a plurality of interconnection lines each formed in the semiconductor circuit region and elongated from an associated one of the third pads to the semiconductor circuit region distantly from the dicing line area.

10. A semiconductor device comprising:

a semiconductor circuit region;

a dicing line area formed around the entire periphery of said semiconductor circuit region;

a characteristic checking element formed in said dicing line area;

a measurement pad formed in said dicing line area, said measurement pad being electrically connected to said characteristic checking element; and

an internal measurement pad formed in the semiconductor circuit region, said internal measurement pad being electrically connected to said characteristic checking element;

wherein said characteristic checking element is configured to be rendered inoperative upon application of a sufficient electric voltage to said internal measurement pad during a semiconductor device test operation.

11. The semiconductor device as claimed in claim 10, wherein said characteristic checking element comprises a checking transistor having a drain, a source and a gate each connected to corresponding one of said measurement pads, the gate being further connected to said internal measurement pad, wherein the gate of said checking transistor is configured to break upon application of said electric voltage.

12. The semiconductor device as claimed in claim 10, wherein said characteristic checking element comprises a plurality of checking transistors each having a drain, a source and a gate, the drains of the checking transistors being connected respectively to different first ones of first pads, said first pads including said measurement pad, the source of the checking transistors being connected in common to a second one of the first pads, the gates of the checking transistors being connected respectively to third pad of the first pads and further to the internal measurement pad, wherein the gate of said checking transistor is configured to break upon application of said electric voltage.

13. The semiconductor device as claimed in claim 10, wherein said characteristic checking element comprises a checking resistance element and a transistor, the checking resistance element having first and second ends connected respectively to two of a plurality of first pads, said first pads including said measurement pad, the transistor having one of drain and source connected to the checking resistance element and a gate connected to the internal measurement pad, wherein the gate of the transistor is configured to break upon application of said electric voltage.

14. The semiconductor device as claimed in claim 10, wherein said characteristic checking element comprising a checking resistance element having first and second ends and a transistor having a gate and first and second diffusion layers, the first and second ends of the checking resistance element being connected respectively to two measurement pads, said two measurement pads including said measurement pad, the gate of the transistor being connected to said internal measurement pad, and the first diffusion layer of the transistor being connected to said checking resistance element, wherein the gate of the transistor is configured to break upon application of said electric voltage.