Array substrate of TFT-LCD and manufacturing method thereof

• US 8,704,231 B2
• Filed: 12/27/2011
• Issued: 04/22/2014
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Sun, Rongge, Ye, Xin
• Primary Examiner(s): Sefer, A.
• Application Number:
  US13/337,665
• Publication Number:
  US 20120161142A1
• Time in Patent Office: 847 Days
• Field of Search: 257/72, 257/59, 438/34
• US Class Current: 257/59
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/122 having a particular pattern
• CPC Class Codes: G02F 2201/15 periodic

Abstract

An array substrate of a TFT-LCD, comprising: a base substrate; gate lines and data lines formed on the substrate, the gate lines and the data lines crossing with each other to define a plurality of pixel units each of which comprises a thin film transistor, a first electrode layer and a second electrode layer, wherein the first electrode layer is separated from the second electrode layer through an insulation layer; the first electrode layer comprises a plurality of first electrodes separated by openings; the second electrode layer comprises a plurality of second electrodes separated by openings; the second electrodes comprise overlapping electrodes each of which completely overlaps with the first electrodes and non-overlapping electrodes whose edges are completely located within an region corresponding to the openings in the first electrode layer.

Claims

1. An array substrate of a thin film transistor liquid crystal display (TFT-LCD), comprising:

a base substrate;

gate lines and data lines formed on the substrate, the gate lines and the data lines crossing with each other to define a plurality of pixel units each of which comprises a thin film transistor, a first electrode layer and a second electrode layer,

wherein the first electrode layer is separated from the second electrode layer through an insulation layer;

the first electrode layer comprises a plurality of first electrodes separated by openings in the first electrode layer;

the second electrode layer comprises a plurality of second electrodes separated by openings in the second electrode layer;

the second electrodes comprise overlapping electrodes each of which completely overlaps with the first electrodes and non-overlapping electrodes whose edges are completely located within an region corresponding to the openings in the first electrode layer; and

the overlapping electrodes and the non-overlapping electrodes are alternately distributed, and

wherein the width “

a”

of each first electrode, the opening width “

b”

of the first electrode layer, the width “

c”

of each second electrode, and the opening width “

d”

of the second electrode layer have the following relationship;

width “

d”

of the second electrode layer have the following relationship;

c+n(c+d)<

a<

c+2d+n(c+d), c<

b<

c+2d, and a+b=2c+2d+n(c+d), wherein “

n”

is an integer greater than or equal to zero.

2. The array substrate of claim 1, wherein the first electrodes serve as a common electrode, and the second electrodes serve as a pixel electrode.

3. The array substrate of claim 1, wherein at least one overlapping electrode is disposed between two neighboring non-overlapping electrodes.

4. The array substrate of claim 1, wherein one overlapping electrode is disposed between two neighboring non-overlapping electrodes, and the width “

a”

of each first electrode, the opening width “

b”

of the first electrode layer, the width “

c”

of each second electrode, and the opening width “

d”

of the second electrode layer have the following relationship;

c<

a<

c+2d, c<

b<

c+2d, and a+b=2c+2d.

5. The array substrate of claim 4, wherein the width “

a”

of each first electrode, the opening width “

b”

of the first electrode layer, the width “

c”

of each second electrode, and the opening width “

d”

of the second electrode layer have the following relationship;

a=b=c+d.

6. The array substrate of claim 1, wherein the first electrode layer is closer to the base substrate than the second electrode layer.