Semiconductor die micro electro-mechanical switch management method

• US 8,704,275 B2
• Filed: 12/28/2007
• Issued: 04/22/2014
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Diamond, Michael B.
• Primary Examiner(s): Fulk, Steven J
• Application Number:
  US12/005,691
• Publication Number:
  US 20080106328A1
• Time in Patent Office: 2,307 Days
• Field of Search: 257/209, 257/254, 257/415, 438/130, 200/181
• US Class Current: 257/209
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H01H 1/0036 Switches making use of microelectromechanical systems [MEMS] for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009
• CPC Class Codes: H01H 2001/0084 with perpendicular movement of the movable contact relative to the substrate
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.

Claims

1. A semiconductor transistor block management method comprising:

supplying electric current to a bus located in a semiconductor die;

closing a micro electro-mechanical switch in a path of said bus; and

opening said micro electro-mechanical switch in said path of said bus, wherein said micro electro mechanical switch selectively couples and decouples a block of transistors to and from a bus, wherein said micro electro mechanical switch includes a plurality of contacts and is configured to make and break a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said buses when said micro electro mechanical switch is open, wherein said plurality of lines are correspondingly coupled to said plurality of contacts.

2. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch prevents electrical current from flowing to said block of transistors when said micro electro-mechanical switch is open.

3. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch is opened when said block of transistors are not being utilized to perform switching operations and closed when said block of transistors are being utilized to perform switching operations.

4. The semiconductor transistor block management method of claim 1 wherein said block of transistors are electrically isolated when said micro electro-mechanical system micro electro-mechanical switch is open.

5. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical system switch permits electrical current to flow to said block of transistors when said micro electro-mechanical system relay switch is closed.

6. The semiconductor transistor block management method of claim 1 wherein said opening and said closing of said electro-mechanical switch is interlinked to other electro-mechanical switches to reduce wear and tear associated with said opening and said closing.

7. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch is included in a micro electro-mechanical relay block.

8. The semiconductor transistor block management method of claim 1 wherein said bus is a power bus and said micro electro-mechanical switch selectively turns power on and off to said block of transistors.

9. The semiconductor transistor block management method of claim 1 wherein said bus is a signal bus and micro electro-mechanical switch selectively permits communication of said signal to said block of transistors.

10. A semiconductor transistor block management method comprising:

supplying electric current to a bus located in a semiconductor die;

closing a micro electro-mechanical switch in a path of said bus, wherein said micro electro-mechanical switch includes a plurality of contacts and said closing includes closing a plurality of connections simultaneously and permits electrical current flow in a plurality of lines in said bus when said micro electro-mechanical switch is closed;

opening said micro electro-mechanical switch in said path of said bus;

wherein said opening includes opening a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said bus when said micro electro-mechanical switch is open;

wherein a plurality of contacts in said micro-electromechanical switch correspond to a plurality of signals and are correspondingly coupled to said plurality of lines.

11. The semiconductor transistor block management method of claim 10 wherein said bus conveys electric current to a transistor if said micro electro-mechanical switch is closed and prevents the flow of current to said transistor if said micro electro-mechanical switch is opened.

12. The semiconductor transistor block management method of claim 10 further comprising:

conveying power to a transistor if said micro electro-mechanical switch is closed; and

preventing power consumption by said transistor if said micro electro-mechanical switch is opened.

13. The semiconductor transistor block management method of claim 10 further comprising:

conveying a signal to a transistor if said micro electro-mechanical switch is closed; and

blocking said transistor from receiving a signal if said micro electro-mechanical switch is opened.

14. The semiconductor transistor block management method of claim 10 further comprising:

receiving an indication of the operations of said block of transistors; and

configuring a state of said micro electro-mechanical switch in accordance with said indication.

15. The semiconductor transistor block management method of claim 10 further comprising:

opening said micro electro-mechanical switch if said components coupled to said bus are not being utilized to perform operations; and

closing said micro electro-mechanical switch if components coupled to said bus are being utilized to perform operations.

16. The semiconductor transistor block management method of claim 10 wherein a plurality of micro electro-mechanical systems switches are included is said path of said bus.

17. A semiconductor transistor block management method comprising:

fabricating a block of transistors in a semiconductor die;

laying a bus in said semiconductor die;

fabricating a micro electro-mechanical switch in the path of said bus on said die in a position to couple and decouple said path of said bus;

wherein said micro electro mechanical switch includes a plurality of contacts and is configured to make and break a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said buses when said micro electro mechanical switch is open, wherein said plurality of lines are correspondingly coupled to said plurality of contacts.

18. The semiconductor transistor block management method of claim 17 further comprising coupling said micro electro-mechanical switch to a control component for controlling operations of said micro electro-mechanical switch.

19. The semiconductor transistor block management method of claim 17 wherein said micro electro-mechanical switch enables hot switching.

20. The semiconductor transistor block management method of claim 17 wherein contacts of said micro electro-mechanical switch are electrically isolated to provided high fidelity and wherein said contacts are electrically isolated by a grounded shield to form a coaxial connection and said contacts of said micro electro-mechanical switch can be configured to make and break a plurality of connections.