Schottky and MOSFET+Schottky structures, devices, and methods

• US 8,704,295 B1
• Filed: 08/17/2011
• Issued: 04/22/2014
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blanchard, Richard A.
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/212,044
• Time in Patent Office: 979 Days
• Field of Search: 257/330, 257/334, 257/341, 257/E29.257
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode.

Claims

1. A semiconductor device, comprising:

trench transistors, each including at least an n-type semiconductor source region and a p-type semiconductor body region defining a junction therebetween;

trench diodes, each including a Schottky barrier where a metallic material touches an n-type semiconductor anode region without making ohmic contact;

one or more semiconductor drift regions, lying at least partially below said body regions and/or said anode regions;

isolation trenches;

shield diffusions lying at least partly beneath said isolation trenches;

wherein at least some ones of said isolation trenches adjoin both a trench transistor and a trench diode;

whereby said shield diffusions reduce electric field at said Schottky barrier, and also at said junction between said source region and said body region.

2. The semiconductor device of claim 1, wherein said isolation trenches each include a respective field plate.

3. The semiconductor device of claim 1, wherein said Schottky barrier is provided by a contact between silicon and a metal silicide.

4. The semiconductor device of claim 1, wherein said Schottky barrier is provided by a contact between a metallic substance and a semiconductor which is doped to less than 10¹⁷ cm⁻

3.

5. The semiconductor device of claim 1, wherein said Schottky barrier is provided by a contact between platinum or titanium silicide and silicon, and is laterally surrounded by a p-type guard ring.

6. The semiconductor device of claim 1, wherein said shield diffusions have a minimum net doping concentration of less than 10¹⁶ cm⁻

3.

7. The semiconductor device of claim 1, wherein said shield diffusions have a maximum net doping concentration of more than 10¹⁷ cm⁻

3 p-type.

8. The semiconductor device of claim 1, wherein said source, body, drift, and drain regions all consist essentially of silicon.

9. The semiconductor device of claim 1, further comprising a frontside metallization which is electrically connected to said source, to said body, and to a metallic portion of said Schottky barrier.

10. The semiconductor device of claim 1, further comprising a back side metallization which is electrically connected to said drain and to a metallic portion of said Schottky barrier.

11. A semiconductor device, comprising:

trench transistors, each including at least an n-type semiconductor source region and a p-type semiconductor body region defining a junction therebetween;

trench diodes, each including a Schottky barrier where a metallic material touches an n-type semiconductor anode region without making ohmic contact, and a p-type guard ring which laterally abuts said Schottky barrier;

one or more semiconductor drift regions, lying at least partially below said body regions and/or said anode regions;

isolation trenches;

shield diffusions lying at least partly beneath said isolation trenches;

wherein at least some ones of said isolation trenches adjoin both a trench transistor and a trench diode;

and wherein said p-type guard ring corresponds to a lateral edge of the same population of dopants as those which form said p-type semiconductor body region;

whereby said shield diffusions reduce electric field at said Schottky barrier, and also at said junction between said source region and said body region.

12. The semiconductor device of claim 11, wherein said shield diffusions have a maximum net doping concentration of more than 10¹⁷ cm⁻

3 p-type.

13. The semiconductor device of claim 11, wherein said source, body, drift, and drain regions all consist essentially of silicon.

14. The semiconductor device of claim 11, further comprising a frontside metallization which is electrically connected to said source, to said body, and to a metallic portion of said Schottky barrier.

15. The semiconductor device of claim 11, further comprising a back side metallization which is electrically connected to said drain and to a metallic portion of said Schottky barrier.

16. A semiconductor device, comprising:

trench transistors, each including at least a semiconductor source region and a semiconductor body region defining a junction therebetween;

trench diodes, each including a Schottky barrier;

isolation trenches;

deep shield diffusions lying at least partly beneath said isolation trenches;

wherein at least some ones of said isolation trenches adjoin both a trench transistor and a trench diode;

whereby said shield diffusions reduce electric field at said Schottky barrier, and also at said junction between said source region and said body region.

17. The device of claim 16, wherein said source regions are n-type semiconductor regions.

18. The semiconductor device of claim 16, wherein said isolation trenches each include a respective field plate.

19. The semiconductor device of claim 16, wherein said Schottky barrier is provided by a contact between silicon and a metal silicide.

20. The semiconductor device of claim 16, wherein said Schottky barrier is provided by a contact between a metallic substance and a semiconductor which is doped to less than 10¹⁷ cm⁻

3.