Devices, methods, and systems with MOS-gated trench-to-trench lateral current flow

• US 8,704,301 B2
• Filed: 12/10/2012
• Issued: 04/22/2014
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Diallo, Mamadou
• Application Number:
  US13/710,006
• Publication Number:
  US 20130119467A1
• Time in Patent Office: 498 Days
• Field of Search: 257335-336, 257/E29.256, 257/E21.418
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained.

Claims

1. A three-dimensional active device structure, comprising:

a downwardly extended source diffusion having a first conductivity type;

a downwardly extended body diffusion having a second conductivity type, and laterally positioned to the source diffusion;

a downwardly extended deep body diffusion having a second conductivity type, and laterally adjoining the body diffusion;

a downwardly extended gate electrode, laterally positioned in proximity to at least part of the body diffusion and insulated from the body diffusion;

a downwardly extended drain, positioned so that the body diffusion is laterally positioned between the drain and the source diffusion;

wherein the source diffusion, body diffusion, deep body diffusion, gate, and drain jointly define a DMOS-type device structure at a horizontal plane; and

wherein the structure has predominately horizontal current flow at the horizontal plane.

2. The structure of claim 1, further comprising a conductor that electrically contacts the drain.

3. The structure of claim 1, further comprising a vertical-walled downwardly-extending trench that is filled with a doped semiconductor material that electrically contacts the drain.

4. The structure of claim 1, wherein the source diffusion, body diffusion, and deep body diffusion consist essentially of a dopant in silicon.

5. The structure of claim 1, wherein the first conductivity type is N-type.

6. The structure of claim 1, wherein the source diffusion and body diffusion are both laterally outdiffused from a single trench.

7. The structure of claim 1, wherein the gate electrode is laterally surrounded by an insulator.

8. The structure of claim 1, wherein at least one of the gate electrode and the drain is formed in a trench that has a depth that is at least 10 times a minimum width of the trench.

9. A three-dimensional active device structure, comprising:

a merged source and body trench;

a downwardly extended source diffusion of a first conductivity type adjacent to walls of the merged source and body trench;

a downwardly extended deep body diffusion of a second conductivity type adjacent to the walls of the merged source and body trench, the second conductivity type opposite the first conductivity type;

a source contact conductor that contacts the source diffusion and deep body diffusion and extends into the merged source and body trench;

a gate trench containing conductive material, the conductive material is capacitively coupled to the deep body diffusion; and

a downwardly extended drain diffusion laterally spaced from the gate trench so as to allow charge carriers from the source diffusion to flow to the drain diffusion under at least some conditions.

10. The structure of claim 9, wherein the merged source and body trench is narrowed at locations where the source diffusion is present.

11. The structure of claim 9, further comprising a conductor that electrically contacts the drain diffusion.

12. The structure of claim 9, further comprising a vertical-walled downwardly-extending trench, filled with a doped semiconductor material that electrically contacts the drain diffusion.

13. The structure of claim 9, wherein the source diffusion and deep body diffusion consist essentially of a dopant in silicon.

14. The structure of claim 9, wherein the first conductivity type is N-type.

15. The structure of claim 9, wherein the source diffusion is laterally surrounded by a body diffusion of the second conductivity type.

16. A three-dimensional active device structure, comprising:

a downwardly extended source diffusion consisting essentially of an N-type dopant in silicon, the source diffusion laterally outdiffused from a first trench;

a downwardly extended body diffusion having a second conductivity type, laterally positioned to the source diffusion, consisting essentially of a dopant in silicon, and laterally outdiffused from the first trench;

a downwardly extended deep body diffusion having a second conductivity type, consisting essentially of a dopant in silicon, and laterally adjoining the body diffusion;

a downwardly extended gate electrode, laterally positioned in proximity to at least part of the body diffusion, and laterally surrounded by an insulator so as to insulate the gate electrode from the body diffusion;

a downwardly extended drain, positioned so that the body diffusion is laterally positioned between the drain and the source diffusion;

a vertical-walled downwardly-extending trench that is filled with a doped semiconductor material that electrically contacts the drain; and

wherein at least one of the gate electrode and the drain is formed in a second trench that has a depth that is at least 10 times a minimum width of the second trench.

17. The structure of claim 16, wherein the source diffusion, body diffusion, deep body diffusion, gate, and drain jointly define a DMOS-type device structure at a horizontal plane.

18. The structure of claim 17, wherein the structure has predominately horizontal current flow at the horizontal plane.