Power semiconductor devices and methods

• US 8,704,302 B2
• Filed: 11/06/2012
• Issued: 04/22/2014
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Paul, Amit, Darwish, Mohamed N.
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/670,019
• Publication Number:
  US 20130299899A1
• Time in Patent Office: 532 Days
• Field of Search: 257/339, 257/E29.201
• US Class Current: 257/339
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.

Claims

1. A power semiconductor device, comprising:

a first-conductivity-type semiconductor substrate, and at least one second-conductivity-type epitaxial layer overlying and forming a junction with said substrate;

at least one trench, extending downwardly into said epitaxial layer, which has dielectric material therein, and also includes vertically graded spatially fixed net electrostatic charge which tends to deplete adjacent second-conductivity-type semiconductor material;

a semiconductor drift region, in said epitaxial layer, which extends down to said junction, and which has a dopant concentration which generally decreases with depth, EXCEPT that an additional concentration of said second-conductivity type dopants is present in said drift region at said junction;

a semiconductor source region, which has said first conductivity type, and a semiconductor body region which has said second conductivity type and which separates said source region from said drift region; and

at least one gate electrode which controls accumulation or depletion of a portion of said body region to thereby define a channel region therein;

wherein, under at least some conditions, majority carriers pass from said source, through said channel and through said drift region to said substrate.

2. The device of claim 1, wherein said first conductivity type is n type.

3. The device of claim 1, wherein said spatially fixed net electrostatic charge comprises implanted ions embedded in a dielectric material.

4. The device of claim 1, wherein said substrate is monocrystalline silicon, and said spatially fixed net electrostatic charge comprises implanted ions embedded in silicon dioxide.

5. The device of claim 1, wherein said semiconductor drift region consists essentially of silicon.

6. The device of claim 1, wherein said spatially fixed net electrostatic charge is lower near the top of said trench than at intermediate depths of said trench.

7. The device of claim 1, wherein the dopant concentration of said drift region decreases with increasing depth.

8. The device of claim 1, wherein the dopant concentration of said drift region decreases with increasing depth, but also increases sharply at the lowest depth of said drain region, in proximity to a metallurgical junction.