Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device

• US 8,704,334 B2
• Filed: 07/19/2011
• Issued: 04/22/2014
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakashiba, Yasutaka
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US13/137,074
• Publication Number:
  US 20110278696A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/428, 257/E29.323, 257/414, 257/427, 257/516, 257/531, 257/679, 257/E21.022, 257/277, 438/48, 438/57, 336/30, 336/200, 323/206, 323/355, 323/232
• US Class Current: 257/531
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.

Claims

1. A semiconductor device, comprising:

a first circuit provided over a substrate;

a first external terminal connected to the first circuit;

a first wire connecting the first circuit and the first external terminal;

a first inductor connected to the first wire;

a second circuit connected to the first circuit;

a second inductor connected to the second circuit;

a second wire connecting the second circuit and the first circuit;

a second external terminal connected to the second wire,

wherein, in a plan view, the second inductor surrounds the first external terminal, the second external terminal, the second circuit, the first circuit, and the first inductor.

2. The semiconductor device according to claim 1, wherein the first circuit comprises a plurality of transistors.

3. The semiconductor device according to claim 1, wherein, in a plan view, the first circuit, the second circuit, the first external terminal, the second external terminal, the first wire, the second wire, the second inductor, and the first inductor are surrounded by a seal ring.

4. The semiconductor device according to claim 1, wherein, in a plan view, the second circuit, the first circuit, the first external terminal, the second external terminal, the first wire, the second wire, and the first inductor are surrounded by a seal ring, and

wherein the second inductor connects to the second circuit through the seal ring.

5. The semiconductor device according to claim 1, wherein the first circuit, the second circuit, the first external terminal, the second external terminal, the first wire, the second wire, and the first inductor are surrounded by a seal ring.

6. The semiconductor device according to claim 1, wherein the substrate comprises a scribe line region to surround a chip formation region, and the second inductor is provided around a seal ring.

7. The semiconductor device according to claim 1, wherein the second inductor is connected to the first circuit through the second circuit.

8. The semiconductor device according to claim 1, wherein the second inductor comprises a first end and a second end that are coupled to the second circuit.

9. The semiconductor device according to claim 1, further comprising:

a seal ring that, in a plan view, is surrounded by the second inductor,

wherein, in a plan view, the seal ring surrounds the first circuit, the second circuit, the first external terminal, the second external terminal, the first wire, the second wire, and the first inductor.

10. The semiconductor device according to claim 9, further comprising:

a chip formation region that, in a plan view, surrounds the seal ring.

11. The semiconductor device according to claim 10, wherein the substrate comprises a scribe line region that, in a plan view, surrounds the chip formation region.

12. The semiconductor device according to claim 1, wherein the first circuit comprises an internal circuit, the second circuit comprises a power supply circuit, the first inductor comprises a signal transmitting/receiving inductor, and the second inductor comprises a power receiving inductor.