Semiconductor packages with thermal dissipation structures and EMI shielding

• US 8,704,341 B2
• Filed: 05/15/2012
• Issued: 04/22/2014
• Est. Priority Date: 05/15/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Lin, I-Chia, Tseng, Yu-Chou, Yang, Jin-Feng, Chung, Chi-Sheng
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US13/472,131
• Publication Number:
  US 20130307128A1
• Time in Patent Office: 707 Days
• Field of Search: 257660-665, 257/E29.282
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/1815 Shape
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.

Claims

1. A semiconductor package, comprising:

a substrate having a grounding element;

a semiconductor chip disposed on the substrate, the semiconductor chip having a plurality of bond pads;

a package body encapsulating the semiconductor chip;

a recess in the package body that exposes at least a portion of an upper surface of the semiconductor chip;

a conductive connecting element disposed in the recess between at least two of the bond pads, wherein the conductive connecting element extends beyond a lateral edge of the semiconductor chip; and

a conductive layer disposed over an outer surface of the package body, wherein the conductive layer directly contacts the conductive connecting element and the grounding element;

wherein a combination of the conductive element and the conductive layer provides thermal dissipation and electromagnetic interference (EMI) shielding for the semiconductor package.

2. The semiconductor package of claim 1, wherein the conductive connecting element directly contacts the upper surface of the semiconductor chip.

3. The semiconductor package of claim 2, wherein a thermal path away from the semiconductor chip extends directly from the chip to the conductive connecting element and directly from the conductive connecting element to the conductive layer.

4. The semiconductor package of claim 1, wherein the recess increases a resonant frequency of the package corresponding to a worst EMI shielding effectiveness so that the resonant frequency exceeds an operating frequency of the semiconductor chip.

5. The semiconductor package of claim 1, wherein the conductive layer directly contacts the upper surface of the semiconductor chip.

6. The semiconductor package of claim 1, wherein the recess comprises a plurality of sub-recesses that are spaced from the upper surface of the semiconductor chip.

7. The semiconductor package of claim 1, wherein the grounding element does not extend all the way through the substrate.

8. The semiconductor package of claim 2, wherein the grounding element comprises a partial via having a sidewall that is exposed from the substrate.

9. A semiconductor package, comprising:

a substrate having a grounding element, wherein the grounding element comprises a partial via having a sidewall that is exposed from the substrate;

a semiconductor chip disposed on the substrate, the semiconductor chip having a plurality of bond pads;

a package body encapsulating the semiconductor chip;

a recess in the package body that exposes at least a portion of the upper surface of the semiconductor chip;

means coupled to the upper surfaces of the semiconductor chip and the package body for providing thermal dissipation and electromagnetic interference (EMI) shielding for the semiconductor package.

10. The semiconductor package of claim 9, wherein the means comprises a recess in the package body above the semiconductor chip, a conductive connecting element disposed within the recess, and a conformal shield over the conductive connecting element.

11. The semiconductor package of claim 10, wherein a thermal path away from the semiconductor chip extends directly from the chip to the conductive connecting element and directly from the conductive connecting element to the conductive layer.

12. The semiconductor package of claim 10, wherein the recess increases a resonant frequency of the package corresponding to a worst EMI shielding effectiveness so that the resonant frequency exceeds an operating frequency of the semiconductor chip.

13. The semiconductor package of claim 9, wherein the means comprises a conformal shield covering the outer surface of the package body and the upper surface of the semiconductor chip exposed by the recess, and a filler within the recess with the conformal shield disposed between the filler and the upper surface of the semiconductor chip.

14. The semiconductor package of claim 13, wherein a thermal path away from the semiconductor chip extends directly from the chip to the conductive connecting element and directly from the conductive connecting element to the conductive layer.

15. The semiconductor package of claim 13, wherein the recess increases a resonant frequency of the package corresponding to a worst EMI shielding effectiveness so that the resonant frequency exceeds an operating frequency of the semiconductor chip.

16. The semiconductor package of claim 9, wherein the means comprises a conductive connecting element covering the upper surface of the semiconductor chip and an upper surface of the package body, and a conformal shield covering the conductive connecting element and the package body.

17. A method of making a semiconductor package, the method comprising:

disposing a semiconductor chip on a substrate, wherein the semiconductor chip has a lateral surface and an upper surface, and the substrate comprises a grounding element;

forming a package body encapsulating the lateral surface of the semiconductor chip, wherein the package body defines a recess exposing the upper surface of the semiconductor chip;

singulating the package body, the substrate, and the grounding element to expose a sidewall of the grounding element; and

forming a conductive layer covering an outer surface of the package body and the upper surface of the semiconductor chip exposed by the recess, and contacting the exposed grounding element.

18. The method of claim 17, wherein the step of forming the conductive layer comprises:

forming a conductive connecting element covering the upper surface of the semiconductor chip; and

forming a conformal shield covering the outer surface of the package body, an upper surface of the conductive connecting element, and contacting the exposed grounding element.

19. The method of claim 17, wherein the step of forming the conductive layer comprises:

forming a conformal shield covering the outer surface of the package body and the upper surface of the semiconductor chip exposed by the recess, and contacting the grounding element; and

forming a filler within the recess.