Integrated circuit package system with exposed interconnects

• US 8,704,349 B2
• Filed: 02/14/2006
• Issued: 04/22/2014
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Chow, Seng Guan, Shim, II Kwon, Han, Byung Joon
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US11/354,806
• Publication Number:
  US 20070190690A1
• Time in Patent Office: 2,989 Days
• Field of Search: 438107-110, 257/686, 257/723, 257/724, 257/777, 257/778, 257/780, 257/E25.006, 257/E25.011, 257/E25.013, 257/E25.027, 257/25.006
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.

Claims

1. A method of manufacture of an integrated circuit package system comprising:

providing a substrate having a first surface and a second surface;

mounting a first set of interconnects to the first surface, the first set of interconnects having exposed top portions and at least partial spheroidal shapes;

mounting a second set of interconnects to the first surface the second set of interconnects having planarized top portions;

mounting an integrated circuit die to the first surface; and

forming an encapsulant on the substrate in two thicknesses around the integrated circuit die and the interconnects, with the exposed top portions protruding above a top surface of the encapsulant and the planarized top portions coplanar with the top surface of the encapsulant.

2. The method as claimed in claim 1 wherein:

forming the encapsulant includes forming the encapsulant having a first thickness around the integrated circuit die and a second thickness around the second set of interconnects.

3. The method as claimed in claim 1 wherein:

forming the encapsulant in two thicknesses includes forming the encapsulant having a first thickness around the second set of interconnects and a second thickness around integrated circuit die, the first thickness is thicker than the second thickness.

4. The method as claimed in claim 1 wherein:

mounting the second set of interconnects further comprises planarizing the second set of interconnects to have the planarized top portions before or after embedding.

5. An integrated circuit package system comprising:

a substrate having a first surface and a second surface;

a first set of interconnects mounted to the first surface, the first set of interconnects having exposed top portions and at least partial spheroidal shapes;

a second set of interconnects mounted to the first surface with the second set of interconnects having planarized top portions;

an integrated circuit die mounted to the first surface; and

an encapsulant on the substrate in two thicknesses around the integrated circuit die and the interconnects, with the exposed top portions protruding above a top surface of the encapsulant and the planarized top portions coplanar with the top surface of the encapsulant.

6. The system as claimed in claim 5 wherein:

the encapsulant includes a first thickness around the integrated circuit die and a second thickness around the second set of interconnects.

7. The system as claimed in claim 5 wherein:

the encapsulant in two thickness includes the encapsulant having a first thickness around the second set of interconnects and a second thickness around the integrated circuit die, the first thickness is thicker than the second thickness.

8. The system as claimed in claim 5 wherein:

the interconnects having a characteristic of being planarized to have the planarized top portions before or after embedding.