Barrier structures and methods for through substrate vias

• US 8,704,375 B2
• Filed: 11/05/2009
• Issued: 04/22/2014
• Est. Priority Date: 02/04/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Chao-Shun, Tseng, Ya-Wen, Chiou, Wen-Chih, Wu, Weng-Jin, Liu, Max
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): CHI, SUBERR L
• Application Number:
  US12/613,417
• Publication Number:
  US 20100193954A1
• Time in Patent Office: 1,629 Days
• Field of Search: 438/637, 438/639, 438/672, 438/675, 438/667, 257/178, 257/669, 257/E23.011, 257/E23.174, 257/774, 257/E23.067, 257/E21.577, 257/E21.585, 257/621, 257/751, 257/E21.597
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.

Claims

1. A semiconductor device comprising:

an active device region disposed between isolation regions in a first substrate;

a through substrate via disposed within the first substrate, the through substrate via being disposed adjacent to the active device region;

a stress barrier layer encircling the through substrate via, wherein the stress barrier layer and the isolation regions extend into the first substrate a substantially same depth; and

a first portion of the first substrate separating the through substrate via from the stress barrier layer forming a buffer layer, the buffer layer surrounding the through substrate via.

2. The device of claim 1, wherein the stress barrier layer comprises oxide or nitride.

3. The device of claim 1, wherein the first substrate comprises a silicon substrate, and wherein the through substrate via comprises a conductive fill material.

4. The device of claim 3, wherein the conductive fill material is lined with a conductive liner, wherein the conductive liner comprises a material selected from the group consisting of titanium, tantalum, tungsten, tungsten carbide, ruthenium, nitrides thereof, and combinations thereof, and wherein the conductive fill comprises a material selected from the group consisting of copper, aluminum, polysilicon, and metal silicides.

5. The device of claim 1, wherein the buffer layer comprises a substantially concentric annular shape centered on a center of the through substrate via.

6. The device of claim 1, wherein a modulus of elasticity of the isolation regions is less than a modulus of elasticity of the buffer layer.

7. The device of claim 1, wherein the modulus of elasticity of the isolation regions is less than 75% of the modulus of elasticity of the buffer layer.

8. The device of claim 1, wherein the thickness of the buffer layer is at least greater than 1% of the diameter or width of the through substrate via.

9. The device of claim 1, further comprising:

a second substrate disposed under a bottom surface of the first substrate and comprising active devices disposed within another isolation regions;

another through substrate via disposed within the second substrate; and

another buffer layer surrounding the another through substrate via, the another isolation regions being separated from the through substrate via by the another buffer layer, wherein the through substrate via and the another through substrate via are coupled together.

10. The device of claim 9, wherein the another buffer layer within the second substrate and the second substrate comprise a same material, and wherein the another buffer layer comprise a substantially concentric annular shape centered on a center of the another through substrate via.

11. A semiconductor device comprising:

an active region disposed between isolation regions disposed within a first surface of a substrate;

a transistor disposed in the active region;

a through substrate via disposed within the substrate, the transistor being disposed adjacent the through substrate via;

an insulating layer surrounding the through substrate via, wherein the insulating layer and the isolation regions have a substantially same depth; and

a portion of the substrate extending to the first surface between the through substrate via and the insulating layer forming a buffer layer, the buffer layer encircling the through substrate via.

12. The device of claim 11, wherein the buffer layer comprises a substantially concentric annular shape centered on a center of the through substrate via.

13. The device of claim 11, wherein the buffer layer is disposed between the isolation regions and the through substrate via, the isolation regions being adjacent the transistor.

14. The semiconductor device of claim 11, wherein the isolation regions and the insulating layer have a same material composition.

15. A semiconductor device comprising:

an active device region surrounded by isolation regions in a substrate;

a through substrate via extending through the substrate, the through substrate via being disposed adjacent the active device region;

a portion of the substrate encircling the through substrate via forming a buffer layer; and

a stress alleviation layer encircling the buffer layer, the stress alleviation layer extending only into an upper portion of the substrate.

16. The semiconductor device of claim 15, wherein the substrate comprises a silicon substrate, wherein the stress alleviation layer comprises an oxide, and wherein the through substrate via comprises a conductive fill material.

17. The semiconductor device of claim 15, wherein the stress alleviation layer further comprises:

a liner material comprising a nitride; and

a filler material comprising an oxide.

18. The semiconductor device of claim 15, wherein the buffer layer and the stress alleviation layer comprise substantially concentric annular shapes centered on a center of the through substrate via.

19. The semiconductor device of claim 15 further comprising a transistor disposed in the active device region.

20. The semiconductor device of claim 15, wherein the wherein the isolation regions and the stress alleviation layer have a same material composition.