Metamaterial power amplifier systems

• US 8,704,593 B2
• Filed: 07/02/2013
• Issued: 04/22/2014
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Hollinworth Fund L.L.C. (Intellectual Ventures LLC)
• Inventors: Dupuy, Alexandre, Gummalla, Ajay, Achour, Maha
• Primary Examiner(s): Choe, Henry
• Application Number:
  US13/933,738
• Publication Number:
  US 20140028401A1
• Time in Patent Office: 294 Days
• Field of Search: 330/126, 330/302, 330/285, 330/296
• US Class Current: 330/126
• CPC Class Codes: H01P 1/2039 Galvanic coupling between Input/Output
• CPC Class Codes: H01P 1/2138 using hollow waveguide filters H01P1/2131 takes precedence
• CPC Class Codes: H01P 5/12 Coupling devices having more than two ports H01P5/04 takes precedence
• CPC Class Codes: H01P 5/20 Magic-T junctions
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/60 Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators H03F3/54 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03H 7/0123 comprising distributed impedance elements together with lumped impedance elements
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/46 Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source for use in multiplex transmission systems H04J1/00
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity.

Claims

1. A bias circuit for biasing a transistor, comprising:

a first transmission line (“

TL”

) having a first end and a second end;

a second TL having a third end and a fourth end;

a third TL comprising a composite right and left handed (“

CRLH”

) structure and having a fifth end and a sixth end;

wherein

the first TL, the second TL and the third TL are coupled radially to form a common portion with the first end, third end and the fifth end;

the first TL is configured to receive a bias signal from an external supply through the second end; and

the second TL is configured to send the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.

2. The bias circuit as in claim 1, wherein

the second TL and the third TL are configured to have a second phase response and a third phase response, respectively, to provide an open circuit at the fourth end of the second TL for signals in a plurality of frequency bands.

3. The bias circuit as in claim 2, wherein

the second TL is configured to have the second phase response to provide arbitrary impedances at the common portion for the signals in the plurality of frequency bands;

and

the third TL is configured based on the CRLH structure to have the third phase response to compensate for the arbitrary impedances.

4. The bias circuit as in claim 3, wherein

the second phase response provides phases for the plurality of frequency bands chosen from k×

180°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is open; and

the third phase response provides phases for the plurality of frequency bands chosen from k×

90°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is shorted.

5. The bias circuit of claim 1, wherein the second TL has a plurality of phase responses.

6. The bias circuit of claim 1, wherein the third TL has a plurality of phase responses.

7. The bias circuit of claim 1, wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.

8. The bias circuit of claim 3, wherein

the second phase response provides phases for the plurality of frequency bands chosen from k×

2x°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end to the plurality of frequency bands when the sixth end is open; and

the third phase response provides phases for the plurality of frequency bands chosen from k×

x°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end to the plurality of frequency bands when the sixth end is shorted;

wherein x represents an angle.

9. A method for operating a bias circuit for biasing a transistor, the bias circuit comprising a first TL having a first end and a second end, a second TL having a third end and a fourth end, a third TL comprising a CRLH structure and having a fifth end and a sixth end, wherein the first TL, the second TL and the third TL are coupled radially to form a common portion with the first end, third end and the fifth end, the method comprising:

receiving, at the first TL, a bias signal from an external supply through the second end; and

sending, from the second TL, the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.

10. The method of claim 9, wherein the second TL has a plurality of phase responses.

11. The method of claim 9, wherein the third TL has a plurality of phase responses.

12. The method of claim 9, further comprising providing, at the fourth end of the second TL, an open circuit in response to signals in a plurality of frequency bands.

13. The method of claim 9, wherein the second TL and the third TL are configured to have a second phase response and a third phase response, respectively, the method further comprising providing an open circuit at the fourth end of the second TL to signals in a plurality of frequency bands.

14. The method as in claim 13, wherein:

the second TL has the second phase response to provide arbitrary impedances at the common portion for the signals in the plurality of frequency bands; and

the third TL has, based on the CRLH structure, the third phase response to compensate for the arbitrary impedances.

15. The method as in claim 13, wherein:

the second phase response provides phases for the plurality of frequency bands chosen from k×

2x°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is open; and

the third phase response provides phases for the plurality of frequency bands chosen from k×

x°

, where k=0, ±

1, ±

2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is shorted;

wherein x is an angle.

16. The method of claim 13, wherein x=90 degrees.

17. A bias circuit for biasing a transistor, comprising:

a first transmission line (“

TL”

) having a first end and a second end;

a second TL having a third end and a fourth end;

means for providing multiple phase responses, said means for providing having a fifth end and a sixth end;

wherein

the first TL, the second TL and the means for providing are coupled radially to form a common portion with the first end, third end and the fifth end;

the first TL is configured to receive a bias signal from an external supply through the second end; and

the second TL is configured to send the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.

18. The bias circuit of claim 17, wherein the second TL has a plurality of phase responses.

19. The bias circuit of claim 17, wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.

20. The bias circuit of claim 17, wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.