Circuit for communication over DC power line using high temperature electronics

• US 8,704,654 B1
• Filed: 06/07/2007
• Issued: 04/22/2014
• Est. Priority Date: 06/07/2007
• Status: Active Grant

• Current Assignee: United States of America as represented by the Administrator of NASA
• Original Assignee: United States Administrator of National Aeronautics and Space Administration
• Inventors: Krasowski, Michael J., Prokop, Norman F.
• Primary Examiner(s): Lee, Benjamin C
• Assistant Examiner(s): Pham, Quang D
• Application Number:
  US11/759,570
• Time in Patent Office: 2,511 Days
• Field of Search: 340/358, 340/538, 455/21, 455/293, 455/309, 455/312, 455/337, 375/324
• US Class Current: 340/538
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 2203/5475 adapted for drill or well combined with data transmission
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02

Abstract

A high temperature communications circuit includes a power conductor for concurrently conducting electrical energy for powering circuit components and transmitting a modulated data signal, and a demodulator for demodulating the data signal and generating a serial bit stream based on the data signal. The demodulator includes an absolute value amplifier for conditionally inverting or conditionally passing a signal applied to the absolute value amplifier. The absolute value amplifier utilizes no diodes to control the conditional inversion or passing of the signal applied to the absolute value amplifier.

Claims

1. A high temperature communications circuit, comprising:

a power conductor for concurrently conducting electrical energy for powering components of the circuit and transmitting a modulated data signal; and

a demodulator for demodulating the modulated data signal and generating a serial bit stream based on the modulated data signal from the power conductor, wherein the demodulator includes a first stage being a capacitively coupled pre-amplifier to amplify alternating current (AC) signal components from the power conductor which include the modulated data signal while blocking the direct current (DC) power, and a second stage comprised of a dual channel circuit whereby the modulated data signal is inverted or non-inverted conditionally to generate an output of each channel of the dual channel circuit upon logic states of first and second externally applied square waves in quadrature whose frequency is determined by a selected crystal driving an oscillator of a processor in communication with the demodulator of the high temperature communications circuit to receive the serial bit stream, wherein the first channel of the dual channel circuit is dedicated to the first square wave applied to the modulated data signal and the second channel of the dual channel circuit is dedicated to the second square wave applied to the modulated data signal;

wherein the demodulator is asynchronous with respect to the modulated data signal and wherein the demodulator includes an absolute value amplifier connected to each channel of the dual channel circuit for conditionally inverting or conditionally passing the output of the second stage applied to the absolute value amplifier, said absolute value amplifier including;

an inverting portion for conditionally inverting the output of the second stage applied to the absolute value amplifier, wherein the inverting portion does not utilizes any diodes and includes an amplifier having an output which is in a negative saturated state when the inverting portion is not inverting the output of the second stage applied to the absolute value amplifier,

a non-inverting portion for conditionally passing the output of the second stage applied to the absolute value amplifier, wherein the non-inverting portion does not utilizes any diodes and includes another amplifier, said other amplifier having an output which is in a negative saturated state when the non-inverting portion is not passing the output of the second stage applied to the absolute value amplifier, and

a summer for summing the outputs of the inverting portion and the non-inverting portion from each channel of the dual channel circuit to output a data signal used for generating said serial bit stream;

wherein the demodulator is adapted for operation in an ambient temperature of at least 200°

C.;

wherein the modulated data signal is an on-off-keyed signal, and the demodulator demodulates the modulated data signal using an asynchronous quadrature detection technique.

2. The circuit as set forth in claim 1, wherein the demodulator comprises a plurality of silicon-on-insulator fabricated semiconductor components.

3. The circuit as set forth in claim 1, wherein the demodulator is resistant to ionizing radiation.

4. The circuit as set forth in claim 3, wherein the demodulator is a radiation hardened device or a strategic radiation hardened device.

5. The circuit as set forth in claim 1, wherein the demodulator contains a third stage comprised of a low pass filter applied to each channel of the dual channel circuit which filters all AC signals to zero which are not at the frequency of the two square waves in quadrature and provides an output of the low pass filter to the respective absolute value amplifier.

6. The circuit as set forth in claim 5, wherein the demodulator contains a fourth stage comprised of the absolute value amplifier connected to each channel of the dual channel circuit to receive the output of the respective low pass filter to generate four channel outputs in which each absolute value amplifier is configured to pass only positive in polarity signals and invert only negative polarity signals of the output of the respective low pass filter.

7. The circuit as set forth in claim 6, wherein the demodulator contains a fifth stage comprised of the summer to combine the aforementioned four channels from the fourth stage.

8. The circuit as set forth in claim 7, wherein the demodulator contains a sixth stage to compare the output from the fifth stage with a reference to generate the serial bit steam.

9. The circuit as set forth in claim 1, further comprising a seventh separate stage whereby the processor of the high temperature communications circuit modulates and transmits an outgoing digital data stream in an on-off keyed fashion on the power conductor.