Power savings technique for LCD using increased frame inversion rate

• US 8,704,743 B2
• Filed: 09/30/2008
• Issued: 04/22/2014
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yao, Wei H., Gettemy, Shawn Robert
• Primary Examiner(s): HARRIS, DOROTHY H
• Application Number:
  US12/286,394
• Publication Number:
  US 20100079509A1
• Time in Patent Office: 2,030 Days
• Field of Search: 345/204, 345 87-104
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general

Abstract

A method and system is disclosed for minimizing parasitic losses associated with a liquid crystal display (LCD) of a device. A frame buffer may be used in conjunction with a driver circuitry integrated circuit. The frame buffer may store a set of display values for the LCD so that the display values corresponding to a plurality of frames may be transmitted together from a processor in a burst. Once the values are transmitted, the processor may idle or hibernate. Alternatively, only the changes to an image may be transmitted from the processor to the driver circuitry. The remaining pixel values may be drawn based on values previously stored in the frame buffer. Furthermore, the driver circuitry may be used to step up the received display rate values to a level that allows for inversion of the polarity of pixels in the LCD using frame inversion.

Claims

1. A method of generating images, comprising:

initializing driver circuitry in a display to receive image data corresponding to voltages to be delivered to pixels in the display at a first display refresh rate;

transmitting the image data from a processor in an electronic device in which the display is located;

receiving the image data at the driver circuitry;

storing the image data in a frame buffer located in the driver circuitry;

generating a first image for display on the display based on the image data;

wherein when the image data is transmitted using a burst transmission over a high speed data connection, generating the first image for display comprises refreshing the first image at a second display refresh rate greater than the first display refresh rate;

when the image data is transmitted using a transmission over a low speed data connection, generating the first image for display comprises refreshing the first image at the first display refresh rate;

wherein the burst transmission comprises transmitting multiple frames of voltages that correspond to the first display refresh rate of the display during a first time period and allowing the processor to idle during a second time period; and

displaying the first image on the display.

2. The method of claim 1, wherein initializing the driver circuitry comprises notifying the driver circuitry of the type of image data to be displayed on the display.

3. The method of claim 1, comprising transmitting an image data request from the display circuitry to the processor when the multiple frames of voltages to be delivered to the pixels in the display have been utilized to generate multiple images for display on the display.

4. The method of claim 3, comprising transmitting secondary image data at the first display refresh rate in the burst transmission from the processor in response to the image data request, wherein the secondary image data corresponds to a second set of multiple frames of voltages to be delivered to the pixels in the display.

5. The method of claim 1, comprising performing a frame inversion for the display once a frame at the second display refresh rate.

6. The method of claim 5, wherein the first display refresh rate is equal to 30 Hz and the second display refresh rate is equal to either 90 Hz or 120 Hz.

7. A display comprising:

image generating circuitry adapted to generate a first image on the display;

a frame buffer located in the display and adapted to store voltage values corresponding to the first image to be generated on the display; and

driver circuitry located in the display and adapted to;

control the image generating circuitry and the frame buffer;

receive the voltage values corresponding to the first image to be generated on the display;

transmit the voltage values to the display to generate an image for display on the display from a processor,

wherein generating the image for display comprises refreshing the image at a first display refresh rate when the voltage values comprise a first amount of data transmitted using a transmission over a low speed data connection;

wherein generating the image for display comprises refreshing the image at a second display refresh rate greater than the first display refresh rate when the voltage values comprise a second amount of data greater than the first amount of data transmitted using a burst transmission over a high speed data connection,

wherein the burst transmission comprises transmitting multiple frames of voltages that correspond to the first display refresh rate of the display during a first time period and allowing the processor to idle during a second time period; and

perform a frame inversion for the display once a frame.

8. The display of claim 7, wherein the frame inversion comprises modulating a voltage transmitted to all pixels in the display.

9. The display of claim 7, wherein the driver circuitry is adapted to receive a second set of voltage values, wherein the second set of voltage values correspond to pixel voltage values to be changed from generation of the first image to generation of a second image.

10. The display of claim 9, wherein the driver circuitry is adapted to process the second set of voltage values with the voltage values to produce a pixel voltage frame corresponding to pixel voltage values for each of a plurality of pixels in the display.

11. The display of claim 10, wherein image generating circuitry is adapted to generate the second image on the display based on the pixel voltage frame.

12. The display of claim 10, wherein the frame buffer is adapted to overwrite the first set of voltage values with the pixel voltage frame.

13. The display of claim 10, wherein processing the second set of voltage values with the first set of voltage values comprises overwriting the voltage values with the second set of voltage values at any overlapping pixel locations.

14. The display of claim 7, wherein the frame buffer is adapted to store voltage values corresponding to a second image to be generated on the display concurrently with the voltage values corresponding to the first image.

15. The display of claim 14, wherein the voltage values corresponding to the first image and the voltage values corresponding to the second image are received by the display circuitry as part of the first time period of the burst transmission.

16. The display of claim 7, wherein the frame buffer comprises a static random access memory.

17. An electronic device, comprising:

a processor adapted to transmit image data as a transmission over a low speed data connection and in a burst transmission over a high speed data connection, wherein the burst transmission comprises transmitting multiple frames of voltages that correspond to the first display refresh rate of the display during a first time period and allowing the processor to idle during a second time period; and

a display, wherein the display comprises;

a frame buffer adapted to store voltage values corresponding to a plurality of images to be generated on the display; and

driver circuitry adapted to;

generate images for display on the display;

wherein when the image data is transmitted using the burst transmission over a high speed data connection, generating the images for display comprises refreshing the images at a second display refresh rate greater than the first display refresh rate;

when the image data is transmitted using the transmission over a low speed data connection, generating the images for display comprises refreshing the images at the first display refresh rate;

perform a frame inversion for the display once a frame; and

update the frame buffer with secondary voltage received via a second burst transmission from the processor, wherein the secondary values correspond to a second plurality of images to be generated on the display.

18. The electronic device of claim 17, wherein the driver circuitry is adapted to transmit an image data request to the processor when voltage values corresponding to a plurality of images to be generated on the display have been utilized to generate multiple images for display on the display.

19. The electronic device of claim 17, wherein the first display refresh rate is equal to 30 Hz and the second display refresh rate is equal to either 90 Hz or 120 Hz.

20. A method of generating an image, comprising:

initializing driver circuitry in a display to receive image data corresponding to voltages to be delivered to pixels in the display at a first display refresh rate;

transmitting voltage values from a processor as a transmission over a low speed data connection and in a burst transmission over a high speed data connection, wherein the voltage values correspond to multiple frames of voltages to be delivered to pixels in a display, and wherein the burst transmission comprises transmitting the multiple frames of voltages that correspond to the first display refresh rate of the display during a first time period and allowing the processor to idle during a second time period;

storing the multiple frames of voltages in a frame buffer located on the display, wherein the frame buffer comprises a static random access memory;

generating a first image for display on the display wherein when the image data is transmitted as the burst transmission over a high speed data connection, generating the first image for display comprises refreshing the first image at a second display refresh rate greater than the first display refresh rate;

when the image data is transmitted as the transmission over a low speed data connection, generating the first image for display comprises refreshing the first image at the first display refresh rate; and

displaying the first image on the display.

21. The method of claim 20, comprising performing a frame inversion for all the pixels in the display for every image displayed at the second display refresh rate.

22. The method of claim 21, wherein performing the frame inversion comprises generating a modulated voltage and transmitting the modulated voltage to all pixels in the display.

23. The method of claim 20, comprising transmitting second voltage values corresponding to new pixel values for any pixels to be changed from the voltage values transmitted in the burst transmission.

24. The method of claim 23, comprising overwriting the voltage values stored in the frame buffer with a combination of the stored voltage values and the second voltage values.