Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit

• US 8,705,263 B2
• Filed: 01/04/2013
• Issued: 04/22/2014
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Tran, Michael
• Application Number:
  US13/734,500
• Publication Number:
  US 20130120023A1
• Time in Patent Office: 473 Days
• Field of Search: 365/94, 365/185.24
• US Class Current: 365/94
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

Claims

1. A programmable non-volatile configuration storage bit circuit on a substrate with a logic circuit, the programmable non-volatile circuit comprising:

a first floating gate associated with a first non-volatile device;

a second floating gate associated with a second non-volatile device;

a first drain region associated with said first non-volatile memory device; and

a second drain region associated with said second non-volatile memory device;

wherein the first drain region and the second drain region overlap respective sufficient portions of said first floating gate and said second floating gate to serve as first and second capacitive couplings, respectively, to the first floating gate and the second floating gate, such that a programming voltage applied to said first drain region or said second drain region can be imparted, respectively, to said first floating gate or said second floating gate through the first capacitive coupling or the second capacitive coupling, respectively;

an output coupled to said first non-volatile device and said second non-volatile device;

wherein a value of said output of said programmable non-volatile circuit is based on a programmed state of said first non-volatile device and said second non-volatile memory device and can be used to configure a function to be performed by the logic circuit.

2. The programmable non-volatile circuit of claim 1 wherein the first and second non-volatile devices are re-channel.

3. The programmable non-volatile circuit of claim 1 wherein at least one of said first floating gate and second floating gate is comprised of a material used as a gate for a transistor device situated on the substrate and associated with at least one of a logic gate or a volatile memory.

4. The programmable non-volatile circuit of claim 1 wherein at least one of said first floating gate and second floating gate can be erased.

5. The programmable non-volatile circuit of claim 4 wherein at least one of said first floating gate and second floating gate can be re-programmed.