Integrated circuit, method for driving the same, and semiconductor device

• US 8,705,267 B2
• Filed: 11/30/2011
• Issued: 04/22/2014
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami, Ohmaru, Takuro
• Primary Examiner(s): Phan, Trong
• Application Number:
  US13/307,060
• Publication Number:
  US 20120140550A1
• Time in Patent Office: 874 Days
• Field of Search: 365/149, 365/154, 365/185.08, 365/220, 365/233.1
• US Class Current: 365/149
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 21/403 Arrangements for storing the counting state in case of power supply interruption
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Claims

1. A circuit comprising:

a first flip-flop; and

a second flip-flop, the second flip-flop including a nonvolatile memory circuit,

wherein in an operating state in which power is supplied to the circuit, the first flip-flop retains data,

wherein in a resting state in which supply of power to the circuit is stopped, the second flip-flop retains data,

wherein on transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop, and

wherein on transition from the resting state into the operating state, the data is transferred from the second flip-flop to the first flip-flop.

2. The circuit according to claim 1 further comprising a selection circuit to which output data from the second flip-flop is input and which selectively outputs any one piece of the data input,

wherein output data from the selection circuit is input to the first flip-flop, and output data from the first flip-flop is input to the second flip-flop.

3. The circuit according to claim 1,

wherein the second flip-flop includes:

a memory circuit that includes a first transistor including an oxide semiconductor in a semiconductor layer and a storage capacitor; and

an arithmetic portion,

wherein in the memory circuit;

output data from the first flip-flop is input to a first electrode of the first transistor;

a second electrode of the first transistor is electrically connected to a first electrode of the storage capacitor;

a second electrode of the storage capacitor is grounded; and

the first electrode of the storage capacitor and the second electrode of the first transistor forms a node,

wherein the arithmetic portion includes a logic circuit,

wherein the logic circuit includes a second transistor whose gate electrode is electrically connected to the node, and

wherein the arithmetic portion performs operation in accordance with data retained in the node.

4. The circuit according to claim 3, wherein the first transistor, and the first flip-flop, the arithmetic portion of the second flip-flop, or the storage capacitor of the second flip-flop are stacked.

5. A semiconductor device comprising the circuit according to claim 1.

6. A circuit comprising a first flip-flop and a second flip-flop, the second flip-flop including a nonvolatile memory circuit,

wherein before a resting state in which supply of power to the first flip-flop and the second flip-flop is stopped, data retained in the first flip-flop is transferred to the second flip-flop,

wherein in the resting state, the data is retained in the second flip-flop, and

wherein after the resting state, the data in the first flip-flop is restored by the second flip-flop.

7. The circuit according to claim 6 further comprising a selection circuit to

which output data from the second flip-flop is input and which selectively outputs any one piece of the data input,

wherein output data from the selection circuit is input to the first flip-flop, and output data from the first flip-flop is input to the second flip-flop.

8. The circuit according to claim 6,

wherein the second flip-flop includes:

a memory circuit that includes a first transistor including an oxide semiconductor in a semiconductor layer and a storage capacitor; and

an arithmetic portion,

wherein in the memory circuit;

output data from the first flip-flop is input to a first electrode of the first transistor;

a second electrode of the first transistor is electrically connected to a first electrode of the storage capacitor;

a second electrode of the storage capacitor is grounded; and

the first electrode of the storage capacitor and the second electrode of the first transistor forms a node,

wherein the arithmetic portion includes a logic circuit,

wherein the logic circuit includes a second transistor whose gate electrode is electrically connected to the node, and

wherein the arithmetic portion performs operation in accordance with data retained in the node.

9. The circuit according to claim 8, wherein the first transistor, and the first flip-flop, the arithmetic portion of the second flip-flop, or the storage capacitor of the second flip-flop are stacked.

10. A semiconductor device comprising the circuit according to claim 6.

11. A method for driving a circuit including a first flip-flop and a second flip-flop, the second flip-flop including a nonvolatile memory circuit, comprising the steps of:

storing first data in the first flip-flop in a first period;

outputting the first data from the first flip-flop and storing the first data in the second flip-flop in a second period after the first period;

stopping supply of power to the circuit in a third period after the second period;

restarting supply of power to the circuit and outputting the first data stored in the second flip-flop in a fourth period after the third period; and

storing the first data in the first flip-flop in a fifth period after the fourth period.

12. The method for driving a circuit according to claim 11 further comprising the steps of:

storing second data in the first flip-flop in a sixth period after the fifth period.

13. A method for driving a circuit including a first flip-flop, a second flip-flop, the second flip-flop including a nonvolatile memory circuit, and a selection circuit comprising the steps of:

outputting first data from the selection circuit and storing the first data in the first flip-flop in a first period;

outputting the first data from the first flip-flop and storing the first data in the second flip-flop in a second period after the first period;

stopping supply of power to the circuit in a third period after the second period;

restarting supply of power to the circuit and outputting the first data stored in the second flip-flop to the selection circuit in a fourth period after the third period; and

outputting the first data from the selection circuit to the first flip-flop and storing the first data in the first flip-flop in a fifth period after the fourth period.

14. The method for driving a circuit according to claim 13 further comprising the steps of:

outputting second data from the selection circuit in a sixth period after the fifth period.

15. A circuit comprising:

a first flip-flop; and

a second flip-flop,

wherein the first flip-flop comprises first transistors, each including a semiconductor material other than an oxide semiconductor in a semiconductor layer,

wherein the second flip-flop comprises a second transistor including an oxide semiconductor in a semiconductor layer,

wherein the second flip-flop includes;

a memory circuit that includes the second transistor and a storage capacitor; and

an arithmetic portion,

wherein one electrode of the second transistor is electrically connected to a first electrode of the storage capacitor,

wherein the arithmetic portion includes a third transistor, and

wherein a gate electrode of the third transistor is electrically connected to the one electrode of the second transistor.

16. The circuit according to claim 15 further comprising a selection circuit which is electrically connected to the first flip-flop and the second flip-flop.

17. The circuit according to claim 15, wherein the second transistor, and the first flip-flop, the arithmetic portion of the second flip-flop, or the storage capacitor of the second flip-flop are stacked.

18. A semiconductor device comprising the circuit according to claim 15.