Nonvolatile memory device and reading method thereof

• US 8,705,279 B2
• Filed: 12/30/2011
• Issued: 04/22/2014
• Est. Priority Date: 10/26/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Se Hyun
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/341,472
• Publication Number:
  US 20130107633A1
• Time in Patent Office: 844 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.22, 365/189.011, 365/189.15, 365/201, 365/230.06, 365/233.17
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the operation of reading data.

Claims

1. A method of reading a nonvolatile memory device, the method comprising:

a read operation of reading data of a selected memory cell;

a first read retry operation of performing one or more read operations by changing a selection read voltage applied to the selected memory cell until the read operation succeeds, when it is detected that an error has occurred in the read operation; and

a second read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the first read retry operation.

2. The method according to claim 1, wherein the selection read voltage applied in the first read retry operation is higher than the selection read voltage applied in the read operation.

3. The method according to claim 2, wherein the selection read voltage is increased whenever the first read retry operation is repeated.

4. The method according to claim 1, wherein the selection read voltage applied in the first read retry operation is lower than the selection read voltage applied in the read operation.

5. The method according to claim 4, wherein the selection read voltage is decreased whenever the first read retry operation is repeated.

6. The method according to claim 1, wherein the non-selection read voltage applied to the non-selected memory cells in the read operation is identical to the non-selection read voltage applied to the non-selected memory cells in the first read retry operation.

7. The method according to claim 1, wherein the non-selection read voltage applied to the non-selected memory cells in the second read retry operation is lower than the non-selection read voltage applied to the non-selected memory cells in the read operation.

8. The method according to claim 7, wherein the non-selection read voltage is decreased whenever the second read retry operation is repeated.

9. The method according to claim 8, wherein the non-selection read voltage applied to the non-selected memory cells in the second read retry operation is higher than the threshold voltage of the selected memory cell in a maximum program state.

10. The method according to claim 1, wherein the selection read voltage applied to the selected memory cell in the read operation is identical to the selection read voltage applied to the selected memory cell in the second read retry operation.

11. A nonvolatile memory device, comprising:

a memory cell array configured to comprise a plurality of memory cells arranged in intersection portions of word lines and bit lines; and

a control logic configured to control a read operation of a selected memory cell among the plurality of memory cells, a first read retry operation of performing one or more read operations by changing a selection read voltage applied to the selected memory cell until the read operation succeeds, when it is detected that an error has occurred in the read operation, and a second read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the first read retry operation.

12. The nonvolatile memory device according to claim 11, wherein the selection read voltage applied in the first read retry operation is higher than the selection read voltage applied in the read operation.

13. The nonvolatile memory device according to claim 11, wherein the selection read voltage applied in the first read retry operation is lower than the selection read voltage applied in the read operation.

14. The nonvolatile memory device according to claim 11, wherein the non-selection read voltage applied to the non-selected memory cells in the read operation is identical to the non-selection read voltage applied to the non-selected memory cells in the first read retry operation.

15. The nonvolatile memory device according to claim 11, wherein the non-selection read voltage applied to the non-selected memory cells in the second read retry operation is lower than the non-selection read voltage applied to the non-selected memory cells in the read operation.

16. The nonvolatile memory device according to claim 15, wherein the non-selection read voltage applied to the non-selected memory cells in the second read retry operation is higher than the threshold voltage of the selected memory cell in a maximum program state.

17. The nonvolatile memory device according to claim 11, wherein the selection read voltage applied to the selected memory cell in the read operation is identical to the selection read voltage applied to the selected memory cell in the second read retry operation.