Memory array circuitry with stability enhancement features
First Claim
1. A method for stabilizing a memory array on an integrated circuit, wherein the memory array contains memory cells that are addressed using address transistors on the memory array and wherein the address transistors comprise body bias terminals, the method comprising:
- testing the memory array with a tester that is coupled to the integrated circuit during testing, wherein testing the memory array comprises performing read tests on the memory array to obtain read test data and performing write tests on the memory array to obtain write test data;
with the tester, analyzing the read test data and the write test data to determine an optimum body bias for the address transistors on the memory array to enhance memory cell stability; and
storing a setting for the optimum body bias in the integrated circuit so that the optimum body bias will be applied to the address transistors on the memory array during normal operation of the integrated circuit.
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Accused Products
Abstract
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.
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Citations
17 Claims
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1. A method for stabilizing a memory array on an integrated circuit, wherein the memory array contains memory cells that are addressed using address transistors on the memory array and wherein the address transistors comprise body bias terminals, the method comprising:
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testing the memory array with a tester that is coupled to the integrated circuit during testing, wherein testing the memory array comprises performing read tests on the memory array to obtain read test data and performing write tests on the memory array to obtain write test data; with the tester, analyzing the read test data and the write test data to determine an optimum body bias for the address transistors on the memory array to enhance memory cell stability; and storing a setting for the optimum body bias in the integrated circuit so that the optimum body bias will be applied to the address transistors on the memory array during normal operation of the integrated circuit. - View Dependent Claims (2, 3, 4)
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5. A method comprising:
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testing a memory array on an integrated circuit with a tester that is coupled to the memory array during testing, wherein the memory array comprises address transistors having body bias terminals and wherein testing the memory array comprises performing read and write tests on the memory array; with the tester, analyzing results from the testing to determine a body bias for the address transistors on the memory array, wherein the results include read and write failures; in response to detecting a read failure, adjusting the body bias in a given direction; in response to detecting a write failure, adjusting the body bias in another direction opposite to the given direction; storing a setting for the body bias in the integrated circuit; and during normal operation of the integrated circuit, outputting static control signals with the memory array. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
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14. A programmable logic device comprising:
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programmable logic on an integrated circuit, wherein the programmable logic is operable to be powered at a core logic power supply voltage; an array of memory cells arranged in rows and columns on the integrated circuit; address lines associated with the rows of the memory cells; data lines associated with the columns of the memory cells; precharge driver circuitry operable to supply a precharge voltage that is less than the core logic power supply voltage to the data lines before memory cell reading operations, wherein the memory cells each comprise at least one address transistor having a body bias terminal, the programmable logic device further comprising; nonvolatile memory on the integrated circuit in which an address transistor body bias setting is stored; and a programmable voltage regulator on the integrated circuit, wherein the programmable voltage regulator is operable to supply a body bias to the body bias terminal of each of the address transistors based on the address transistor body bias setting stored in the nonvolatile memory. - View Dependent Claims (15, 16, 17)
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Specification