Memory array circuitry with stability enhancement features

• US 8,705,300 B1
• Filed: 08/04/2010
• Issued: 04/22/2014
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Xu, Yanzhong, Watt, Jeffrey T.
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Reidlinger, Lance
• Application Number:
  US12/850,528
• Time in Patent Office: 1,357 Days
• Field of Search: 365/154, 365/156, 365/201
• US Class Current: 365/201
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.

Claims

1. A method for stabilizing a memory array on an integrated circuit, wherein the memory array contains memory cells that are addressed using address transistors on the memory array and wherein the address transistors comprise body bias terminals, the method comprising:

testing the memory array with a tester that is coupled to the integrated circuit during testing, wherein testing the memory array comprises performing read tests on the memory array to obtain read test data and performing write tests on the memory array to obtain write test data;

with the tester, analyzing the read test data and the write test data to determine an optimum body bias for the address transistors on the memory array to enhance memory cell stability; and

storing a setting for the optimum body bias in the integrated circuit so that the optimum body bias will be applied to the address transistors on the memory array during normal operation of the integrated circuit.

2. The method defined in claim 1 wherein testing the memory array comprises performing the read and write tests at various address transistor body biases.

3. The method defined in claim 1 further comprising:

identifying a maximum acceptable body bias voltage above which read failures occur; and

identifying a minimum acceptable body bias voltage below which write failures occur.

4. The method defined in claim 1 wherein the integrated circuit comprises a nonvolatile memory and a programmable voltage regulator that is controlled by the nonvolatile memory and wherein storing the setting comprises storing the setting for the optimum body bias in the nonvolatile memory so that the programmable voltage regulator applies the optimum body bias to the address transistors.

5. A method comprising:

testing a memory array on an integrated circuit with a tester that is coupled to the memory array during testing, wherein the memory array comprises address transistors having body bias terminals and wherein testing the memory array comprises performing read and write tests on the memory array;

with the tester, analyzing results from the testing to determine a body bias for the address transistors on the memory array, wherein the results include read and write failures;

in response to detecting a read failure, adjusting the body bias in a given direction;

in response to detecting a write failure,

adjusting the body bias in another direction opposite to the given direction;

storing a setting for the body bias in the integrated circuit; and

during normal operation of the integrated circuit, outputting static control signals with the memory array.

6. The method of claim 5 further comprising:

applying the body bias to the address transistors on the memory array.

7. The method defined in claim 5, wherein testing the memory array comprises identifying read failures and write failures at various address transistor body biases.

8. The method defined in claim 5 further comprising:

identifying a maximum acceptable body bias voltage above which read failures occur.

9. The method defined in claim 5 further comprising:

identifying a minimum acceptable body bias voltage below which write failures occur.

10. The method defined in claim 5, wherein the integrated circuit comprises a nonvolatile memory, and wherein storing the setting comprises storing the setting for the body bias in the nonvolatile memory.

11. The method defined in claim 5, wherein the integrated circuit comprises a programmable voltage regulator, the method further comprises:

applying the body bias to the address transistors on the memory array with the programmable voltage regulator.

12. The method defined in claim 5 further comprising:

applying the body bias to the address transistors on the memory array during normal operation of the integrated circuit, wherein the tester is not coupled to the integrated circuit during normal operation.

13. The method defined in claim 5, wherein the integrated circuit further comprises voltage regulator circuitry, and wherein testing the memory array on the integrated circuit with the tester comprises:

sending control signals from the tester to the voltage regulator circuitry on the integrated circuit.

14. A programmable logic device comprising:

programmable logic on an integrated circuit, wherein the programmable logic is operable to be powered at a core logic power supply voltage;

an array of memory cells arranged in rows and columns on the integrated circuit;

address lines associated with the rows of the memory cells;

data lines associated with the columns of the memory cells;

precharge driver circuitry operable to supply a precharge voltage that is less than the core logic power supply voltage to the data lines before memory cell reading operations, wherein the memory cells each comprise at least one address transistor having a body bias terminal, the programmable logic device further comprising;

nonvolatile memory on the integrated circuit in which an address transistor body bias setting is stored; and

a programmable voltage regulator on the integrated circuit, wherein the programmable voltage regulator is operable to supply a body bias to the body bias terminal of each of the address transistors based on the address transistor body bias setting stored in the nonvolatile memory.

15. The programmable logic device defined in claim 14 wherein the body bias that the programmable voltage regulator is operable to supply to the body bias terminal of each of the address transistors comprises a positive body bias.

16. The programmable logic device defined in claim 14 wherein the body bias that the programmable voltage regulator is operable to supply to the body bias terminal of each of the address transistors comprises a negative body bias.

17. The programmable logic device defined in claim 14 wherein the precharge driver circuitry comprises a plurality of precharge drivers, wherein a respective one of the precharge drivers is connected to each of the data lines, wherein each precharge driver includes an n-channel metal-oxide-semiconductor transistor, wherein the memory cells are dual-port memory cells, and wherein the at least one address transistor having a body bias terminal comprises four address transistors each having a body bias terminal.