State-monitoring memory element

• US 8,705,309 B2
• Filed: 06/11/2013
• Issued: 04/22/2014
• Est. Priority Date: 04/17/2007
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sheets, Michael, Williams, Timothy John
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/915,464
• Publication Number:
  US 20130336081A1
• Time in Patent Office: 315 Days
• Field of Search: 365226-229, 365/189.09, 365/154
• US Class Current: 365/228
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC'"'"'s state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.

Claims

1. An apparatus comprising:

a state-monitoring memory element comprising a first power supply connection and a second power supply connection between which is applied an input voltage supply;

a circuit element coupled to the state-monitoring memory element to effectuate a voltage drop in the input voltage supply to provide a degraded voltage supply between the first power supply connection and the second power supply connection of the state-monitoring element, wherein the circuit element is configured to cause the state-monitoring memory element to lose a logic state before a normal memory element when the input voltage supply drops below a threshold value; and

a failure detection element coupled to the state-monitoring element, wherein the failure detection element is configured to detect a failure by the state-monitoring memory element to retain the logic state and, responsive to the detection, to generate an indication of the failure.

2. The apparatus of claim 1, wherein the circuit element comprises a voltage supply circuit configured to provide a degraded input supply voltage on the first power supply connection that results in the degraded voltage supply being applied between the first power supply connection and the second power supply connection of the state-monitoring element.

3. The apparatus of claim 2, wherein the voltage supply circuit comprises at least one of a diode or a transistor device.

4. The apparatus of claim 1, wherein the circuit element comprises a voltage supply circuit configured to provide a degraded ground on the second power supply connection that results in the degraded voltage supply being applied between the first power supply connection and the second power supply connection of the state-monitoring element.

5. The apparatus of claim 4, wherein the voltage supply circuit comprises at least one of a diode or a transistor device.

6. The apparatus of claim 1, wherein the circuit element comprises at least one of a diode, a transistor device, or a current source.

7. The apparatus of claim 1, wherein the state-monitoring memory element is at least one of a register, a memory cell, a latch, an array of registers, or an array of memory cells.

8. The apparatus of claim 1, wherein the failure detection element is adapted to issue a reset signal responsive to detecting the failure in the state-monitoring memory element.

9. The apparatus of claim 1, wherein the failure detection element is adapted to issue an interrupt to a system processor with an indication of the failure responsive to detecting the failure in the state-monitoring memory element.

10. An integrated circuit comprising:

a state-monitoring memory element comprising a first power supply connection and a second power supply connection between which is applied an input voltage supply;

a plurality of normal memory elements;

a circuit element coupled to the state-monitoring memory element to effectuate a voltage drop in the input voltage supply to provide a degraded voltage supply between the first power supply connection and the second power supply connection of the state-monitoring element, wherein the circuit element is configured to cause the state-monitoring memory element to lose a logic state before the plurality of normal memory elements when the input voltage supply drops below a threshold value; and

a failure detection element coupled to the state-monitoring element, wherein the failure detection element is configured to detect a failure by the state-monitoring memory element to retain the logic state and, responsive to the detection, to generate an indication of the failure.

11. The integrated circuit of claim 10, wherein the state-monitoring memory element and the plurality of normal memory elements are at least one of registers, memory cells, or latches.