Generating and implementing a signal protocol and interface for higher data rates

• US 8,705,579 B2
• Filed: 06/02/2004
• Issued: 04/22/2014
• Est. Priority Date: 06/02/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, Jon James, Steele, Brian, Wiley, George Alan, Shekhar, Shashank
• Primary Examiner(s): GREY, CHRISTOPHER P
• Application Number:
  US10/860,116
• Publication Number:
  US 20050021885A1
• Time in Patent Office: 3,611 Days
• Field of Search: 370/389, 370/503, 370509-514, 375/365, 375/366, 375/368
• US Class Current: 370/514
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/245 by using the properties of transmission codes
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 65/70 Media network packetisation
• CPC Class Codes: H04L 69/03 Protocol definition or specification protocol conformance testing H04L1/244
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/24 Negotiation of communication capabilities
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04M 1/72412 using two-way short-range wireless interfaces
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/41407 embedded in a portable device, e.g. video client on a mobile phone, PDA, laptop constructional details of equipment or arrangements specially adapted for portable computer application G06F1/1626; arrangements specially adapted for mobile receivers in broadcast systems H04H20/57
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Claims

1. A state machine for use in obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the state machine configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, comprising:

a circuit to change synchronization states, the synchronization states comprising the at least one Acquiring Sync States synchronization states and at least two In-Sync States synchronization states;

the circuit to change synchronization states comprising configuring the circuit for changing from a first Acquiring Sync State to a first In-Sync State comprising a no-sync state transitioning to the first In-Sync State based on detecting a presence of a synchronization pattern and a good CRC at a subframe boundary;

the circuit to change synchronization states comprising configuring the circuit for changing from the first In-Sync State to a next In-Sync State comprising detecting the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data; and

the circuit to change synchronization states comprising configuring the circuit for changing from the next In-Sync State to the first In-Sync State comprises detecting a presence of a single good CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data.

2. The state machine of claim 1, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises detecting the presence of no synchronization pattern or a bad CRC value at a sub-frame boundary.

3. The state machine of claim 1, wherein one condition for changing between a first In-Sync State or a next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises detecting the presence of a predetermined number of consecutive bad CRC values.

4. A method for obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the system configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, the method comprising the steps of:

changing from a first Acquiring Sync State to a first In-Sync State by transitioning from a no sync state to the first In-Sync State by detecting a presence of a synchronization pattern and a good CRC at a subframe boundary by a processor;

changing from the first In-Sync State to a next In-Sync State by detecting the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data by the processor; and

changing from the next In-Sync State to the first In-Sync State by detecting a presence of a single good CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data by the processor.

5. The method of claim 4, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises the step of detecting the presence of no synchronization pattern or a bad CRC value at a sub-frame boundary.

6. The method of claim 4, wherein one condition for changing between a first In-Sync State or next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises the step of detecting the presence of a predetermined number of consecutive bad CRC values.

7. A non-transitory storage media comprising program instructions which are hardware computer-executable to implement synchronization in an electronic system for transferring digital data at a high rate between a host device and a client device over a communication path, the system configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, the storage media comprising:

program instructions that cause a change from a first Acquiring Sync State to a first In-Sync State by a transition from a no sync state to the first In-Sync State by a detection of a presence of a synchronization pattern and a good CRC at a subframe boundary;

program instructions that cause a change from the first In-Sync State to a next In-Sync State by the detection of the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data; and

program instructions that cause a change from the next In-Sync State to the first In-Sync State by the detection of the presence of a single good CRC value without using a synchronization pattern, based on the calculated CRC value for every packet of the transferred digital data.

8. The storage media of claim 7, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises program instructions that cause the detection of the presence of no synchronization pattern or a bad CRC value at the sub-frame boundary.

9. The storage media of claim 7, wherein one condition for changing between a first In-Sync State or next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises program instructions that cause the detection of the presence of a predetermined number of consecutive bad CRC values.