Timing phase detection using a matched filter set

• US 8,705,673 B2
• Filed: 09/05/2008
• Issued: 04/22/2014
• Est. Priority Date: 09/05/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Noeldner, David
• Primary Examiner(s): Ahn, Sam K
• Assistant Examiner(s): Ali, Shawkat M
• Application Number:
  US12/205,811
• Publication Number:
  US 20100061490A1
• Time in Patent Office: 2,055 Days
• Field of Search: 375/346, 375/371, 370/338, 379/399, 360/29, 360/39, 360/46, 360/51
• US Class Current: 375/346
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 25/03248 Arrangements for operating in conjunction with other apparatus
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033

Abstract

Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.

Claims

1. A method for utilizing data decoding circuitry to determine clock phase, the method comprising:

providing a matched filter bank, wherein the matched filter bank is operable to receive a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence;

receiving a timing pattern;

re-tuning the first matched filter to detect a first pattern corresponding to the timing pattern sampled using a first phase of the sample clock; and

re-tuning the second matched filter to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock.

2. The method of claim 1, wherein the method further comprises:

comparing an output of the first matched filter with an output of the second matched filter to determine whether the sample clock is closer to the first phase or the second phase.

3. The method of claim 2, wherein the method further comprises:

modifying the phase of the sample clock based at least in part on the determination of whether the sample clock is closer to the first phase or the second phase.

4. The method of claim 1, wherein the method further comprises:

re-tuning the first matched filter to detect the first bit sequence in the series of symbols and to assert the first symbol proxy upon detection of the first bit sequence; and

re-tuning the second matched filter to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence.

5. The method of claim 1, wherein the timing pattern is a 4T preamble associated with a data transfer from a magnetic storage medium.

6. The method of claim 1, wherein the matched filter bank further includes a third matched filter tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and a fourth matched filter tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence.

7. The method of claim 6, wherein the method further comprises:

re-tuning the third matched filter to detect a third pattern corresponding to the timing pattern sampled using a third phase of the sample clock; and

re-tuning the fourth matched filter to detect a fourth pattern corresponding to the timing pattern sampled using a fourth phase of the sample clock.

8. The method of claim 7, wherein the method further comprises:

comparing an output of the first matched filter, an output of the second matched filter, and output of the third matched filter and an output of the fourth matched filter to determine whether the sample clock is closer to the first phase, the second phase, the third phase or the fourth phase.

9. The method of claim 8, wherein the method further comprises:

modifying the phase of the sample clock based at least in part on the determination of whether the sample clock is closer to the first phase, the second phase, the third phase or the fourth phase.

10. The method of claim 1, wherein the method further comprises:

receiving an analog input;

performing an analog to digital conversion on the analog input, wherein a series of digital samples are formed synchronous to the sample clock;

providing a noise filter, wherein the noise filter receives and filters the series of digital samples;

and bypassing the noise filter when the timing pattern is received.

11. A timing phase adjustment circuit, the circuit comprising:

a bank of matched filters, wherein the bank of matched filters includes a first matched filter tuned to detect a first pattern corresponding to a timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock; and

a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.

12. The circuit of claim 11, wherein the first matched filter and the second matched filter are finite impulse response filters.

13. The circuit of claim 11, wherein the timing pattern is a 4T preamble associated with a data transfer from a magnetic storage medium.

14. The circuit of claim 11, wherein the circuit further includes an analog to digital converter operable to receive an analog input and to provide a series of digital samples synchronous to the sample clock.

15. The circuit of claim 14, wherein the series of digital samples is provided to the first matched filter and the second matched filter.

16. A communication system including a receiver with a phase timing adjustment circuit, the system comprising:

a receiver, wherein the receiver includes;

an analog to digital converter operable to receive an analog input and to provide a series of digital samples synchronous to a sample clock, and wherein the series of digital samples correspond to a timing pattern;

a bank of matched filters, wherein the bank of matched filters is operable to receive the series of digital samples, wherein the bank of matched filters includes a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock; and

a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.

17. The system of claim 16, wherein the analog signal is transmitted by a transmitter to the receiver via a transfer medium, wherein the system is a hard disk drive system, and wherein the transfer medium is a magnetic storage medium.

18. The system of claim 17, wherein the timing pattern is a 4T preamble associated with a data transfer from the magnetic storage medium.

19. The system of claim 16, wherein the analog signal is transmitted by a transmitter to the receiver via a transfer medium, wherein the communication system is a wireless communication system, and wherein the transfer medium is an atmosphere through which a radio frequency signal is transmitted.

20. The system of claim 16, wherein the system further includes a detector circuit, and wherein the detector circuit is operable to perform a Viterbi algorithm detection on a series of outputs provided from a combination of the first matched filter and the second matched filter.