Techniques for processor/memory co-exploration at multiple abstraction levels

• US 8,706,453 B2
• Filed: 10/09/2012
• Issued: 04/22/2014
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Nohl, Achim, Hoffmann, Andreas, Braun, Gunnar, Zerres, Olaf W. J.
• Primary Examiner(s): Phan, Thai
• Application Number:
  US13/648,251
• Publication Number:
  US 20130124183A1
• Time in Patent Office: 560 Days
• Field of Search: 703/2, 703/14, 711/100, 716/4, 716/104, 716/105, 717/139
• US Class Current: 703/2
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.

Claims

1. A computer readable medium storing computer executable instructions that when executed by at least one processor cause the processor to:

form a functional level architecture description language (ADL) communication protocol of a processor and memory co-simulation from composition and sequencing of a first set of primitives; and

form a cycle-accurate level architecture description language (ADL) communication protocol of said processor and memory co-simulation from composition and sequencing of a second set of primitives.

2. The computer readable medium as recited in claim 1, wherein the instructions further comprise instructions to generate a functional processor and memory co-simulation model including a functional interface for said first set of primitives.

3. The computer readable medium as recited in claim 1, wherein the instructions further comprise instructions to generate a cycle-accurate processor and memory co-simulation model including a cycle-accurate interface for said second set of primitives.

4. The computer readable medium as recited in claim 2, wherein said functional interface comprises a read primitive, and wherein memory access is performed immediately.

5. The computer readable medium as recited in claim 4, wherein said functional interface further comprises a write primitive, and wherein memory access is performed immediately.

6. The computer readable medium as recited in claim 2, wherein a memory access request is achieved with a single primitive in said first set of primitives using said functional interface, and wherein said single primitive is selected between a read primitive and a write primitive.

7. The computer readable medium as recited in claim 3, wherein said cycle-accurate interface comprises a request-based interface.

8. The computer readable medium, as recited in claim 3, wherein said cycle-accurate interface comprises separate primitives in said second set of primitives for requesting and completing a memory access.

9. A computer readable medium storing computer executable instructions that when executed by at least one processor cause the processor to:

form one or more communication protocols by composition and sequence of one or more memory interface primitives;

generate a processor and memory co-simulation, including a processor simulation model, a memory simulation model and a communication interface at one or more of a plurality of abstraction levels, from an Architecture Description Language (ADL) description of a processor, an ADL description of a memory system and the one or more communication protocols.

10. The computer readable medium as recited in claim 9, wherein said one or more of the plurality of abstraction levels comprise a functional level.

11. The computer readable medium as recited in claim 9, wherein said one or more of the plurality of abstraction levels comprise a cycle-accurate level.

12. The computer readable medium as recited in claim 9, wherein said processor simulation model is attachable to a memory simulation environment by adapting said communication protocol to said memory simulation environment.

13. A computer readable medium storing computer executable instructions that when executed by at least one processor cause the processor to:

generate a first set of primitives operable for composition and sequencing to form a first communication protocol used with a functional level architecture description language (ADL) of a processor and a memory;

generate a second set of primitives operable for composition and sequencing to form a second communication protocol used with a cycle-accurate level architecture description language (ADL) of said processor and said memory; and

store said first and second set of primitives on a computing device readable medium as a set of application program interfaces (APIs).

14. The computer readable medium as recited in claim 13, wherein the instructions further comprise instructions to:

input said functional level ADL description of said processor and said memory to an automatic simulation generation tool to generate a functional one of a processor and memory simulation model including a functional interface comprising said first set of primitives.

15. The computer readable medium as recited in claim 14, wherein said functional interface comprises a read primitive, and wherein memory access is performed immediately.

16. The computer readable medium as recited in claim 15, wherein said functional interface further comprises a write primitive, and wherein memory access is performed immediately.

17. The computer readable medium as recited in claim 15, wherein a memory access request is achieved with a single primitive in said first set of primitives using said functional interface, and wherein said single primitive is selected between a read primitive and a write primitive.

18. The computer readable medium as recited in claim 13, wherein the instructions further comprise instructions to:

input said cycle-accurate ADL description of said processor and said memory to said automatic simulation generation tool to generate a cycle-accurate one of a processor and memory simulation model including a cycle-accurate interface comprising said second set of primitives.

19. The computer readable medium as recited in claim 18, wherein said cycle-accurate interface comprises a request-based interface.

20. The computer readable medium as recited in claim 18, wherein said cycle-accurate interface comprises separate primitives in said second set of primitives for requesting and completing a memory access.