Implementing mixed-precision floating-point operations in a programmable integrated circuit device

• US 8,706,790 B1
• Filed: 03/03/2009
• Issued: 04/22/2014
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): Sandifer, Matthew
• Application Number:
  US12/396,720
• Time in Patent Office: 1,876 Days
• Field of Search: 708/501, 708/503, 708/523, 708620-632
• US Class Current: 708/513
• CPC Class Codes: G06F 2207/3812 Devices capable of handling different types of numbers
• CPC Class Codes: G06F 2207/3824 Accepting both fixed-point and floating-point numbers
• CPC Class Codes: G06F 2207/5356 Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator
• CPC Class Codes: G06F 7/487 Multiplying; Dividing G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

The resources needed—particularly in a programmable device—when carrying out a mixed-precision multiplication-based floating-point operation (i.e., multiplication or division) is reduced by maintaining the mantissas of the operands in their native precisions instead of promoting the lower-precision number to the higher precision. Exponents and other elements can be handled by the higher-precision logic as they do not consume significant resources.

Claims

1. A method of configuring a programmable integrated circuit device to perform a multiplication-based floating-point operation on a first input value of a first precision defined by an industry standard and represented by a first number of bits, and a second input value of a second precision, defined by said industry standard, different in precision from said first precision defined by said industry standard, and represented by a second number of bits different in count from said first number, wherein said programmable integrated circuit device incorporates multiplier circuits, said method comprising:

configuring logic of said programmable integrated circuit device to break up said multiplication-based floating-point operation into one or more multiplication operations on different portions of said first and second input values of said first and second precisions defined by said industry standard;

configuring logic of said programmable integrated circuit device to break up, for each one of said one or more multiplication operations, each different portion of said first input value of said first precision defined by said industry standard into a first plurality of input segments of a certain size and each different portion of said second input value of said second precision defined by said industry standard into a second plurality of input segments of the certain size;

configuring logic of said programmable integrated circuit device for using a quantity of said multiplier circuits to multiply said first plurality of input segments by said second plurality of input segments; and

configuring logic of said programmable integrated circuit device to combine outputs of all said multiplier circuits.

2. The method of claim 1 wherein said multiplication-based operation is multiplication.

3. The method of claim 1 wherein said multiplication-based operation is division.

4. The method of claim 1 further comprising configuring logic of said programmable integrated circuit device to discard a least significant one of said input segments.

5. The method of claim 1 wherein:

one of said first and second input values is a floating-point number and another of said first and second input values is a fixed-point number;

said method further comprising;

converting said another of said first and second input values into a floating-point number.

6. The method of claim 1 wherein:

said first input value has a first mantissa and a first exponent, and said second input value has a second mantissa and a second exponent; and

said multiplier circuits operate on said first and second mantissas to provide a mantissa of a product of said input values;

said method further comprising;

configuring general-purpose programmable logic of said programmable integrated circuit device to operate on said first and second exponents to provide an exponent of said product of said input values.

7. A programmable integrated circuit device configured to perform a multiplication-based floating-point operation on a first input value of a first precision defined by an industry standard and represented by a first number of bits, and a second input value of a second precision defined by said industry standard, different in precision from said first precision defined by said industry standard, and represented by a second number of bits different in count from said first number, wherein said programmable integrated circuit device incorporates multiplier circuits, said configured programmable integrated circuit device comprising:

logic configured to break up said multiplication-based floating-point operation into one or more multiplication operations on different portions of said first and second input values of said first and second precisions defined by said industry standard;

logic configured to break up, for each one of said one or more multiplication operations, each different portion of said first precision defined by said industry standard into a first plurality of input segments of a certain size and each different portion of said second input value of said second precision defined by said industry standard into a second plurality of input segments of the certain size;

logic configured to use a quantity of said multiplier circuits to multiply said first plurality of input segments by said second plurality of input segments; and

logic configured to combine outputs of all said multiplier circuits.

8. The programmable integrated circuit device of claim 7 wherein said multiplication-based operation is multiplication.

9. The programmable integrated circuit device of claim 7 wherein said multiplication-based operation is division.

10. The programmable integrated circuit device of claim 7 further comprising logic configured to discard a least significant one of said input segments.

11. The programmable integrated circuit device of claim 7 wherein:

one of said first and second input values is a floating-point number and another of said first and second input values is a fixed-point number;

said programmable integrated circuit device further comprising;

logic configured to convert said another of said first and second input values into a floating-point number.

12. The programmable integrated circuit device of claim 7 wherein:

said first input value has a first mantissa and a first exponent, and said second input value has a second mantissa and a second exponent; and

said multiplier circuits operate on said first and second mantissas to provide a mantissa of a product of said input values;

said programmable integrated circuit device further comprising;

general-purpose programmable logic of said programmable integrated circuit device configured to operate on said first and second exponents to provide an exponent of said product of said input values.

13. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform a multiplication-based floating-point operation on a first input value of a first precision defined by an industry standard and represented by a first number of bits, and a second input value of a second precision defined by said industry standard, different in precision from said first precision defined by said industry standard, and represented by a second number of bits different in count from said first number, wherein said programmable integrated circuit device incorporates multiplier circuits, said instructions comprising:

instructions to configure logic of said programmable integrated circuit device to break up said multiplication-based floating-point operation into one or more multiplication operations on different portions of said first and second input values of said first and second precisions defined by said industry standard;

instructions to configure logic of said programmable integrated circuit device to break up, for each one of said one or more multiplication operations, each different portion of said first input value of said first precision defined by said industry standard into a first plurality of input segments of a certain size and each different portion of said second input value of said second precision defined by said industry standard into a second plurality of input segments of the certain size;

instructions to configure logic of said programmable integrated circuit device for using a quantity of said multiplier circuits to multiply said first plurality of input segments by said second plurality of input segments; and

instructions to configure logic of said programmable integrated circuit device to combine outputs of all said multiplier circuits.

14. The non-transitory machine-readable data storage medium of claim 13 wherein said multiplication-based operation configured by said instructions is multiplication.

15. The non-transitory machine-readable data storage medium of claim 13 wherein said multiplication-based operation configured by said instructions is division.

16. The non-transitory machine-readable data storage medium of claim 13 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device to discard a least significant one of said input segments.

17. The non-transitory machine-readable data storage medium of claim 13 wherein:

one of said first and second input values is a floating-point number and another of said first and second input values is a fixed-point number;

said instructions further comprising;

instructions to configure logic of said programmable integrated circuit device to convert said another of said first and second input values into a floating-point number.

18. The non-transitory machine-readable data storage medium of claim 13 wherein:

said first input value has a first mantissa and a first exponent, and said second input value has a second mantissa and a second exponent; and

said instructions configure said multiplier circuits operate on said first and second mantissas to provide a mantissa of a product of said input values;

said instructions further comprising;

instructions to configure general-purpose programmable logic of said programmable integrated circuit device to operate on said first and second exponents to provide an exponent of said product of said input values.