Memory system

• US 8,706,950 B2
• Filed: 02/27/2009
• Issued: 04/22/2014
• Est. Priority Date: 03/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yano, Junji, Matsuzaki, Hidenori, Hatsuda, Kosuke
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US12/394,875
• Publication Number:
  US 20090222617A1
• Time in Patent Office: 1,880 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Claims

1. A memory system comprising:

a volatile memory that stores data of a sector size;

a nonvolatile semiconductor memory from which data is read out in a page size and in which data is erased in a block size twice or a larger natural number times as large as the page size;

a controller that controls the nonvolatile semiconductor memory, and manages data stored in the nonvolatile semiconductor memory in a first management size which is larger than the sector size and smaller than the page size;

a first table that has registered an information of first failure areas of the first management size that have occurred in the nonvolatile semiconductor memory as a first number; and

a second table that has registered an information of second failure areas of the block size that have occurred in the nonvolatile semiconductor memory as a second number;

wherein the controller is configured to;

register the information of the first failure areas in the first table, if the controller fails to correct errors of the data of the first management size when reading out the data from the nonvolatile semiconductor memory;

register the information of the second failure areas in the second table, if an erasing operation is finished by a first mode when erasing the data from the nonvolatile semiconductor memory; and

switch an operation mode to a read only mode and to not start processing for a data writing request even when the controller receives the data writing request from a host apparatus when the first number becomes larger than a first value or when the second number becomes larger than a second value.

2. The memory system according to claim 1, wherein the controller switches, based on the first number, the operation mode to one of any modes chosen from:

a write back mode;

a write through mode; and

the read only mode.

3. The memory system according to claim 2, wherein

the controller switches from the write back mode to the write through mode when the first number is equal to or larger than a first threshold value.

4. The memory system according to claim 3, wherein

the controller switches from the write through mode to the read only mode when the first number is equal to or larger than a second threshold value which is larger than the first threshold value.

5. The memory system according to claim 2, wherein

the controller switches from the write through mode to the read only mode when a number of free areas of the block size is insufficient in the nonvolatile semiconductor memory.

6. The memory system according to claim 1, wherein

the controller switches, based on the second number, the operation mode to one of any modes chosen from:

a write back mode;

a write through mode; and

the read only mode.

7. The memory system according to claim 6, wherein

the controller switches from the write back mode to the write through mode when the second number is equal to or larger than a third threshold value.

8. The memory system according to claim 7, wherein

the controller switches from the write through mode to the read only mode when the second number is equal to or larger than a fourth threshold value which is larger than the third threshold value.

9. The memory system according to claim 6, wherein

the controller switches from the write through mode to the read only mode when a number of free areas of the block size is insufficient in the nonvolatile semiconductor memory.

10. The memory system according to claim 1, wherein

the controller further includes an error correction circuit which is capable of correcting error in data of the first management size which is read out from the nonvolatile semiconductor memory, wherein when the error correction circuit fails in the error correction, the controller registers the data of the first management size as the failure areas of the first management size.

11. The memory system according to claim 1, wherein

when an erasing operation in an area of the block size is finished by the first mode, the controller registers the area of the block size as the failure areas of the block size.

12. The memory system according to claim 2, wherein

in the write back mode, the controller writes data, which is input from the host apparatus, in the volatile memory, and flushes the data stored in the volatile memory to the nonvolatile semiconductor memory when the predetermined condition is satisfied.

13. The memory system according to claim 2, wherein

in the write through mode, after writing the data input from the host apparatus into the volatile memory, the controller forcibly flushes the data stored in the volatile memory to the nonvolatile semiconductor memory.

14. The memory system according to claim 2, wherein

in the read only mode, the controller returns an error message without executing a data writing request.

15. The memory system according to claim 1, wherein

the controller manages the data stored in a first storage area of the nonvolatile semiconductor memory by the first management size, and manages the data stored in a second storage area of the nonvolatile semiconductor memory by a second management size which is larger than the page size and smaller than the block size.

16. The memory system according to claim 15, wherein

the second management size is twice or larger natural number times as large as the first management size.

17. The memory system according to claim 2, wherein to restore a state before power-off, when initialization of the memory system fails, the controller switches to a protection mode from at least one of modes:

the write back mode;

the write through mode; and

the read only mode.

18. A memory system comprising:

a nonvolatile semiconductor memory from which data is read out in a first size and in which data is erased in a second size;

a first table that has registered an information of first failure areas of a first management size that have occurred in the nonvolatile semiconductor memory as a first number;

a second table that has registered an information of second failure areas of a second management size that have occurred in the nonvolatile semiconductor memory as a second number; and

a controller configured to;

register the information of the first failure areas in the first table, if the controller fails to correct errors of the data of the first management size when reading out the data from the nonvolatile semiconductor memory;

register the information of the failure areas in the second table, if an erasing operation is finished by a first mode when erasing the data from the nonvolatile semiconductor memory; and

switch an operation mode to a read only mode and to not start processing for a data writing request even when the controller receives the data writing request from a host apparatus when the first number becomes larger than a first value or when the second number becomes larger than a second value.

19. The memory system according to claim 18, wherein, based on the first number,

the controller switches the operation mode to one of any modes chosen from:

a write back mode;

a write through mode; and

the read only mode.

20. The memory system according to claim 18, further comprising a volatile memory that stores data of a sector size, wherein

the controller controls data transfer between the volatile memory and the nonvolatile semiconductor memory.