Deterministic management of dynamic thermal response of processors

• US 8,707,060 B2
• Filed: 10/31/2008
• Issued: 04/22/2014
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rotem, Efraim, Rajwan, Doron, Finkelstein, Lev
• Primary Examiner(s): REHMAN, MOHAMMED H
• Application Number:
  US12/263,431
• Publication Number:
  US 20100115293A1
• Time in Patent Office: 1,999 Days
• Field of Search: None
• US Class Current: 713/300
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed.

Claims

1. A processor comprising:

first logic to determine power consumption values by the processor during a first time period, wherein the power consumption values and one or more thermal design power (TDP) values corresponding to the first time period are to be stored in memory; and

second logic to determine a power level budget for the processor based on the power consumption values, one or more variations in inter-processor core communication activity, and the one or more TDP values, wherein the power level budget is to indicate whether the processor may exceed the one or more TDP values, wherein the first logic is to determine the power consumption values at least for a thermally significantly time interval, wherein a timer is to generate a signal indicative of a sampling rate, wherein the first logic is to determine the power consumption values at the sampling rate.

2. The processor of claim 1, where the one or more TDP values are to be loaded during run time.

3. The processor of claim 1, wherein the power level budget is to indicate whether the processor may exceed the one or more TDP values during a second time period.

4. The processor of claim 3, wherein the second time period is to follow the first time period.

5. The processor of claim 1, further comprising a plurality of cores, wherein at least one of the cores comprises the second logic.

6. The processor of claim 5, wherein the second logic is to determine a power level budget for more than one of the plurality of cores.

7. The processor of claim 5, wherein the second logic is to determine a power level budget for a sum of power consumption by the plurality of cores.

8. The processor of claim 5, further comprising third logic to cause a change to a voltage level supplied to at least one of the plurality of cores and/or an operating frequency of at least one of the plurality of cores based on the power level budget.

9. The processor of claim 1, further comprising one or more sensors to detect variations, corresponding to components of the processor, in one or more of:

operating frequency or operating voltage of one or more components of the processor, temperature, and power consumption.

10. The processor of claim 1, further comprising third logic to cause a change to a voltage level supplied to the processor and/or an operating frequency of the processor based on the power level budget.

11. The processor of claim 1, wherein a voltage regulator is to supply power to the processor.

12. The processor of claim 1, wherein the second logic, the first logic, and the memory are on a single integrated circuit.

13. The processor of claim 1, wherein the first logic is to track architectural activity to predict values in addition to or instead of actual measurements.

14. The processor of claim 1, wherein the first logic is to track a state of the processor to predict values in addition to or instead of actual measurements.

15. The processor of claim 1, wherein the one or more variations in inter-processor core communication activity are to be detected by one or more sensors.

16. The processor of claim 1, wherein the thermally significant time interval is to be determined based on a heat sink thermal response time interval.

17. A method comprising:

determining power consumption values by a processor during a first time period, wherein the power consumption values and one or more thermal design power (TDP) values corresponding to the first time period are stored; and

determining a power level budget for the processor based on the power consumption values, one or more variations in inter-processor core communication activity, and the one or more TDP values, wherein the power level budget indicates whether the processor may exceed the one or more TDP values, wherein the processor determines the power consumption values at least for a thermally significantly time interval, wherein a timer generates a signal indicative of a sampling rate, wherein the processor determines the power consumption values at the sampling rate.

18. The method of claim 17, further comprising causing a change to a voltage level supplied to the processor and/or an operating frequency of the processor based on the power level budget, wherein the power level budget is to indicate whether the processor may exceed the one or more TDP values during a second time period.

19. The method of claim 17, further comprising detecting variations, corresponding to components of the processor, in one or more of:

operating frequency or operating voltage of one or more components of the processor, temperature, and power consumption.

20. The method of claim 17, further comprising determining a power level budget for more than one core of the processor.

21. The method of claim 17, further comprising generating a signal indicative of a sampling rate, wherein determining the power consumption values is performed at the sampling rate.

22. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

determine power consumption values by a processor during a first time period;

store the power consumption values and one or more thermal design power (TDP) values corresponding to the first time period; and

determine a power level budget for the processor based on the power consumption values, one or more variations in inter-processor core communication activity, and the one or more TDP values, wherein the power level budget indicates whether the processor may exceed the one or more TDP values, wherein the processor determines the power consumption values at least for a thermally significantly time interval, wherein a timer generates a signal indicative of a sampling rate, wherein the processor determines the power consumption values at the sampling rate.

23. The computer-readable medium of claim 22, further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to cause a change to a voltage level supplied to the processor and/or an operating frequency of the processor based on the power level budget, wherein the power level budget is to indicate whether the processor may exceed the one or more TDP values during a second time period.

24. The computer-readable medium of claim 22, further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to detect variations, corresponding to components of the processor, in one or more of:

operating frequency or operating voltage of one or more components of the processor, temperature, and power consumption.

25. The computer-readable medium of claim 22, further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to determine a power level budget for more than one core of the processor.

26. The computer-readable medium of claim 22, further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to generate a signal indicative of a sampling rate, wherein determining the power consumption values is performed at the sampling rate.

27. A system comprising:

a processor having a plurality of processor cores, wherein power consumption values by the processor during a first time period and one or more thermal design power (TDP) values corresponding to the first time period are to be stored and wherein the processor is to comprise;

first logic to determine the power consumption values; and

second logic to determine a power level budget for one or more of the plurality of processor cores based on the power consumption values, one or more variations in inter-processor core communication activity, and the one or more TDP values, wherein the power level budget is to indicate whether the one or more processor cores may exceed the one or more TDP values during a second time period following the first time period, wherein the first logic is to determine the power consumption values at least for a thermally significantly time interval, wherein a timer is to generate a signal indicative of a sampling rate, wherein the first logic is to determine the power consumption values at the sampling rate; and

a voltage regulator to supply power to the plurality of processor cores.

28. The system of claim 27, further comprising third logic to cause a change to a voltage level supplied to at least one of the plurality of cores and/or an operating frequency of at least one of the plurality of cores based on the power level budget.

29. The system of claim 27, further comprising a power source coupled to the processor via the voltage regulator.

30. The system of claim 27, further comprising third logic coupled between the second logic and the first logic.

31. The system of claim 27, further comprising one or more sensors to detect variations, corresponding to one or more of the plurality of processor cores, in one or more of:

operating frequency, operating voltage, temperature, and power consumption.

32. The system of claim 27, further comprising an audio device.