3D structured memory devices and methods for manufacturing thereof

• US 8,709,894 B2
• Filed: 09/16/2011
• Issued: 04/29/2014
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Ki Hong, Pyi, Seung Ho, Kwon, Il Young, Bin, Jin Ho
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US13/234,422
• Publication Number:
  US 20130069152A1
• Time in Patent Office: 956 Days
• Field of Search: 257/390, 438/268
• US Class Current: 438/268
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Claims

1. A method of forming a n+ region and a p+ region at a source/drain region, the method comprising:

forming a n+ doped region over an undoped channel material in a recess;

removing a horizontal portion of the n+ region in the recess to expose a surface of the undoped channel material;

forming a diffusion barrier material over the exposed surface of the undoped channel material and the n+ region in the recess;

removing a horizontal portion of the diffusion barrier material in the recess to expose the upper surface of the undoped channel material; and

forming a p+ region adjacent to the diffusion barrier material in the recess.

2. The method of claim 1, wherein forming a diffusion barrier material comprises forming a dielectric layer.

3. The method of claim 1, wherein forming a diffusion barrier material comprises forming a metal layer.

4. The method of claim 1, wherein forming a p+ region adjacent to the diffusion barrier material comprises:

forming a p+ doped poly-silicon over the undoped channel material and the diffusion barrier material in the recess; and

planarizing the p+ doped poly-silicon.

5. The method of claim 1, wherein forming the p+ region adjacent to the diffusion barrier material comprises:

forming an undoped poly-silicon over the undoped channel poly-silicon, the n+ region, and the diffusion barrier material;

planarizing the undoped poly-silicon; and

implanting a p-type dopant into the undoped poly-silicon.

6. The method of claim 1, wherein removing a horizontal portion of the n+ region in the recess to expose a surface of the undoped channel material comprises removing the horizontal portion of the n+ region in the recess and removing an upper portion of the undoped channel material below the recess to expose the surface of the undoped channel material.