Manufacturing method power semiconductor device

• US 8,709,895 B2
• Filed: 03/01/2011
• Issued: 04/29/2014
• Est. Priority Date: 11/04/2010
• Status: Active Grant

• Current Assignee: Sinopower Semiconductor, Inc.
• Original Assignee: Sinopower Semiconductor, Inc.
• Inventors: Tai, Sung-Shan, Tsai, Hung-Sheng
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/038,346
• Publication Number:
  US 20120112268A1
• Time in Patent Office: 1,155 Days
• Field of Search: 438/270, 438/589, 257/330, 257/E21.419, 257/E29.258
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.

Claims

1. A manufacturing method of a power semiconductor device, comprising:

providing a semiconductor substrate, the semiconductor substrate having at least one first trench and a second trench, and the semiconductor substrate having an active region and a termination region, the first trench being disposed in the active region, the second trench disposed in the termination region, wherein the semiconductor substrate has a first conductive type;

forming a gate structure in the first trench, wherein the gate structure comprises a first insulating layer and a gate conductive layer;

forming a second insulating layer to cover the semiconductor substrate, the first trench being filled up with the second insulating layer, and the second insulating layer being filled into the second trench;

removing the first insulating layer and the second insulating layer outside the first trench and the second trench to expose a part of the semiconductor substrate;

forming a doped body region and a doped source region in the exposed semiconductor substrate, wherein the doped body region has a second conductive type, and the doped source region is disposed in the doped body region and has the first conductive type;

forming an interlayer dielectric layer to cover the semiconductor substrate;

forming at least one first contact hole in the interlayer dielectric layer and the doped source region in the active region and forming a second contact hole in the interlayer dielectric layer and the doped source region in the termination region, wherein the second trench is disposed between the second contact hole and the first trench; and

forming a source metal layer and a gate metal layer on the interlayer dielectric layer, so that the source metal layer is electrically connected to the doped source region, and the gate metal layer is electrically connected to the gate conductive layer.

2. The manufacturing method of a power semiconductor device according to claim 1, wherein the step of forming the gate structure comprises:

forming a first insulating layer to cover the semiconductor substrate, and the first insulating layer covering the first trench and the second trench; and

filling a gate conductive layer into the second trench.

3. The manufacturing method of a power semiconductor device according to claim 2, wherein the step of filling the gate conductive layer comprises:

depositing a conductive layer on the first insulating layer, the first trench being filled up with the conductive layer, and the second trench being partially filled with the conductive layer; and

performing an isotropic etching process to remove the conductive layer outside the first trench, so that the first trench is filled with the gate conductive layer.

4. The manufacturing method of a power semiconductor device according to claim 1, wherein a width of the second trench is substantially 5 to 20 times as large as a width of the first trench.

5. The manufacturing method of a power semiconductor device according to claim 1, wherein the second trench is filled up with the second insulating layer.

6. The manufacturing method of a power semiconductor device according to claim 1, wherein the step of forming the second insulating layer utilizes a high density plasma (HDP) chemical vapor deposition (CVD) process.

7. The manufacturing method of a power semiconductor device according to claim 1, wherein a material of forming the second insulating layer comprises oxide, borophosphosilicate glass (BPSG), tetra-ethyl-ortho-silicate (TEOS) or a combination of oxide and TEOS.

8. The manufacturing method of a power semiconductor device according to claim 1, wherein the step of removing the first insulating layer and the second insulating layer outside the first trench and the second trench comprises a chemical mechanical polishing (CMP) process or a photolithography and etching process.

9. The manufacturing method of a power semiconductor device according to claim 1, wherein the step of forming the first contact hole and the second contact hole further comprises a hole in the interlayer dielectric layer on the second trench.

10. The manufacturing method of a power semiconductor device according to claim 9, further comprising forming a drain metal layer on the interlayer dielectric layer in the termination region, and the second contact hole and the hole being filled up with the drain metal layer.

11. The manufacturing method of a power semiconductor device according to claim 1, wherein after forming the first contact hole and the second contact hole, the manufacturing method comprises performing an ion implantation process to form a doped contact region in the doped body region exposed by the first contact hole and the second contact hole respectively.

12. The manufacturing method of a power semiconductor device according to claim 1, wherein the first contact hole is filled up with the source metal layer.

13. The manufacturing method of a power semiconductor device according to claim 1, further comprising forming a drain metal layer on the interlayer dielectric layer in the termination region, and the second contact hole being filled up with the drain metal layer.