Vertical gate LDMOS device

• US 8,709,899 B2
• Filed: 08/10/2012
• Issued: 04/29/2014
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A., Lu, Yang, Fatemizadeh, Badredin, Prasad, Jayasimha, Paul, Amit, Ruan, Jun, Xia, John
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/572,281
• Publication Number:
  US 20130109143A1
• Time in Patent Office: 627 Days
• Field of Search: 438/270, 438/286, 438/589, 438/FOR.190, 257/E21.621
• US Class Current: 438/286
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

Claims

1. A method of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

depositing a masking layer on an n-well region implanted on a substrate;

patterning the masking layer to define an area;

forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region;

filling the first trench with a conductive material;

depositing a layer of oxide over the area;

etching out at least a portion of the layer of oxide to expose a portion of the conductive material;

removing the conductive material from the exposed portion to form a second trench; and

filling the second trench with an oxide to form an asymmetric gate of the vertical LDMOS transistor.

2. The method of claim 1, further comprising oxidizing a bottom of the first trench prior to filling the first trench with the conductive material.

3. The method of claim 2, further comprising depositing a layer of nitride on a sidewall of the first trench prior to oxidizing the bottom of the first trench, wherein the sidewall abuts the n-well region.

4. The method of claim 1, wherein the masking layer comprises a conductive material.

5. The method of claim 4, wherein the conductive material is polysilicon.

6. The method of claim 1, wherein the masking layer comprises an oxide.

7. The method of claim 1, wherein the etching through the second masking layer leaves residual spacers that abut the first masking layer in the area.

8. The method of claim 7, further comprising removing at least one of the spacers.

9. The method of claim 1, wherein a width of the second trench at the surface of the n-well region is at least half a width of the first trench at the surface of the n-well region.

10. The method of claim 1, further comprising forming at least a portion of p-body of the vertical LDMOS transistor after forming the first trench.

11. The method of claim 10, further comprising implanting a p-type material in the n-well region through the first trench using a first p-type implant beam.

12. The method of claim 11, further comprising neutralizing a portion of the implanted p-type material using an n-type implant beam, wherein an energy of the n-type implant beam is less than an energy of the p-type implant beam.

13. The method of claim 1, further comprising implanting into a source region of the transistor, a p-body region.

14. The method of claim 13, further comprising:

implanting, into the source region of the transistor, an n+ region and a p+ region, in the p-body region; and

implanting, into a drain region of the transistor, an n+ region.

15. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

depositing a first masking layer on an n-well region implanted on a substrate;

patterning the first masking layer to define an area;

depositing a second masking layer over the area;

etching through the second masking layer in a first portion of the area to expose the n-well region;

etching the exposed n-well region to form a first trench such that the first trench extends from a surface of the n-well region to a first depth in the n-well region;

filling the first trench by a first gate material;

etching through the second masking layer in a second portion of the area to expose at least a portion of the n-well region

depositing a third masking layer over the area;

etching through a first portion of the third masking layer to expose a portion of the first gate material;

removing the first gate material from the exposed portion to form a second trench that extends from the surface of the n-well region to a second depth that is greater than the first depth; and

filling the second trench with a second gate material to form an asymmetric gate of the LDMOS transistor.

16. The method of claim 15, further comprising oxidizing a bottom of the first trench prior to filling the first trench with the first gate material.

17. The method of claim 16 further comprising depositing a layer of nitride on a sidewall of the first trench prior to oxidizing the bottom of the first trench, wherein the sidewall abuts the n-well region.

18. The method of claim 15, wherein the first masking layer comprises an oxide.

19. The method of claim 15, wherein the first masking layer comprises a nitride.

20. The method of claim 18, wherein the second masking layer comprises a nitride.

21. The method of claim 15, wherein the etching through the second masking layer leaves residual spacers that abut the first masking layer in the area.

22. The method of claim 21, further comprising removing at least one of the spacers.

23. The method of claim 15, wherein the first gate material comprises a conductive material.

24. The method of claim 23, wherein the second gate material comprises a dielectric material.

25. The method of claim 15, wherein the first gate material comprises a dielectric material.

26. The method of claim 25, wherein the second gate material comprises a conductive material.

27. The method of claim 15, further comprising forming at least a portion of p-body of the vertical LDMOS transistor after forming the first trench.

28. The method of claim 27, wherein forming the portion of the p-body comprises implanting a p-type material in the n-well region through the first trench using a first p-type implant beam.

29. The method of claim 28, further comprising neutralizing a portion of the implanted p-type material using an n-type implant beam, wherein energy of the n-type implant beam is less than the energy of the p-type implant beam.

30. The method of claim 15, further comprising implanting into a source region of the transistor, a p-body region.

31. The method of claim 30, further comprising:

implanting an n+ region and a p+ region in the p-body region; and

implanting, into a drain region of the transistor, an n+ region.