Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

• US 8,709,903 B2
• Filed: 09/05/2013
• Issued: 04/29/2014
• Est. Priority Date: 11/30/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Joseph, Alvin J., Levy, Max G., Phelps, Richard A., Slinkman, James A., Wolf, Randy L., Ellis-Monaghan, John J.
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/018,814
• Publication Number:
  US 20140004687A1
• Time in Patent Office: 236 Days
• Field of Search: 438149-166, 438/295, 438/311, 438404-409, 438/458, 438/459, 438479-481, 438/967, 257/E29.287, 257347-354
• US Class Current: 438/311
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Claims

1. A method of forming a semiconductor structure comprises:

forming a semiconductor substrate having a first surface and a second surface opposite said first surface;

forming an insulator layer on and immediately adjacent to said second surface;

performing additional processing so as to form in said semiconductor substrate;

a first portion immediately adjacent to said first surface and comprising, in a first concentration, a dopant having a given conductivity type such that said first portion has said given conductivity type; and

,

a second portion extending vertically from immediately adjacent to said first portion to said second surface immediately adjacent to said insulator layer and comprising, in a second concentration greater than said first concentration, one of a same dopant as said dopant in said first portion, a different dopant than said dopant in said first portion, wherein said different dopant has said given conductivity type, and a combination of said same dopant as said dopant in said first portion and said different dopant than said dopant in said first portion such that said second portion has said given conductivity type at a higher conductivity level than said first portion; and

,

forming a device layer on said insulator layer, said device layer comprising multiple semiconductor devices and said first portion and said second portion of said semiconductor substrate each extending laterally and continuously so as to traverse below each of said multiple semiconductor devices.

2. The method of claim 1, further comprising:

implanting gas ions into said second portion; and

,

heating said semiconductor substrate so as to create, from said gas ions, micro-cavities in said second portion.

3. The method of claim 1, said additional processing being performed such that said first portion has a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion has a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

4. The method of claim 1, said additional processing being performed such that said second portion suppresses formation of a parasitic inversion charge layer at said first surface and, thereby reduces harmonic behavior.

5. A method of forming a semiconductor structure comprises:

forming a semiconductor substrate having a first surface and a second surface opposite said first surface, said forming of said semiconductor substrate comprising, during said forming of said semiconductor substrate, doping said semiconductor substrate with a first concentration of a dopant having a given conductivity type;

forming an insulator layer on and immediately adjacent to a second surface of said substrate above said first surface;

implanting one of said dopant and a different dopant having said given conductivity type into said semiconductor substrate to a predetermined depth below said second surface such that, after said implanting, said semiconductor substrate comprises;

a first portion immediately adjacent to said first surface and comprising, in said first concentration, said dopant; and

a second portion extending vertically from said predetermined depth to said second surface and comprising, in a second concentration higher than said first concentration, one of said dopant and a combination of said dopant and said different dopant such that said second portion has said given conductivity type at a higher conductivity level than said first portion; and

,

forming a device layer on said insulator layer, said device layer comprising multiple semiconductor devices and said first portion and said second portion of said semiconductor substrate each extending laterally and continuously so as to traverse below each of said multiple semiconductor devices.

6. The method of claim 5, further comprising:

implanting gas ions into said second portion; and

,

heating said semiconductor substrate so as to create, from said gas ions, micro-cavities in said second portion.

7. The method of claim 5, said implanting being performed such that said first portion has a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion has a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

8. The method of claim 5, said implanting being performed such that said second portion suppresses formation of a parasitic inversion charge layer at said first surface and, thereby reduces harmonic behavior.

9. A method of forming a semiconductor structure comprises:

forming a semiconductor substrate having a first surface and a second surface opposite said first surface;

forming an insulator layer on and immediately adjacent to said second surface;

performing additional processing so as to form in said semiconductor substrate;

a first portion immediately adjacent to said first surface and comprising, in a first concentration, a dopant having a given conductivity type such that said first portion has said given conductivity type; and

a second portion extending vertically from said first portion to said second surface and comprising said dopant in a second concentration greater than said first concentration such that said second portion has said given conductivity type at a higher conductivity level than said first portion; and

,

forming a device layer on said insulator layer, said device layer comprising multiple semiconductor devices and said first portion and said second portion of said semiconductor substrate each extending laterally and continuously so as to traverse below each of said multiple semiconductor devices.

10. The method of claim 9, further comprising:

implanting gas ions into said second portion; and

,

heating said semiconductor substrate so as to create, from said gas ions, micro-cavities in said second portion.

11. The method of claim 9, said additional processing being performed such that said first portion has a resistance of at least 10 ohm-centimeters (Ω

-cm).

12. The method of claim 9, said additional processing further being performed such that said second portion has a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

13. The method of claim 9, said additional processing being performed such that said second portion suppresses formation of a parasitic inversion charge layer at said first surface and, thereby reduces harmonic behavior.

14. The method of claim 9, said semiconductor substrate comprising a silicon substrate, said insulator layer comprising an oxide layer on said second surface of said silicon substrate and said method further comprising forming a silicon layer on said oxide layer such that said silicon layer is separated from said second portion of said silicon substrate by said oxide layer.