Method for manufacturing semiconductor device

• US 8,709,920 B2
• Filed: 02/16/2012
• Issued: 04/29/2014
• Est. Priority Date: 02/24/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Yuta, Noda, Kosei
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/397,839
• Publication Number:
  US 20120217499A1
• Time in Patent Office: 803 Days
• Field of Search: 438/195, 438/176, 438/157, 438/257
• US Class Current: 438/479
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A method for forming a U-shaped vertically long groove in a region where a channel portion of a transistor is formed to make a channel length longer than an apparent channel length additionally requires a photolithography process for forming a groove; therefore, it has a problem in terms of costs and yield. By forming a three-dimensional channel region with the use of a gate electrode or a structure having an insulating surface, a channel length is made three times or more, preferably five times or more, further preferably ten times or more as long as a channel length when seen from the above.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode;

forming a gate insulating film over the gate electrode;

forming a semiconductor film which is over the gate insulating film; and

forming a pair of electrodes over the gate insulating film so that the pair of electrodes does not overlap with the gate electrode and is in contact with the semiconductor film,

wherein a thickness of the gate electrode is selected so that a channel length is three times or more as long as an apparent channel length which is a distance between the pair of electrodes when seen from above.

2. The method for manufacturing a semiconductor device, according to claim 1,

wherein the pair of electrodes is formed over the semiconductor film.

3. The method for manufacturing a semiconductor device, according to claim 1,

wherein an oxide semiconductor film is formed as the semiconductor film.

4. The method for manufacturing a semiconductor device, according to claim 1,

wherein a plasma treatment is performed on at least one of the pair of electrodes and the gate electrode.

5. The method for manufacturing a semiconductor device, according to claim 4,

wherein the plasma treatment is a reverse sputtering treatment.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first gate electrode;

forming a second gate electrode over the first gate electrode so that a top surface of the second gate electrode is smaller than a top surface of the first gate electrode;

forming a gate insulating film over the second gate electrode;

forming a semiconductor film which is over the gate insulating film; and

forming a pair of electrodes over the gate insulating film so that the pair of electrodes does not overlap with the second gate electrode and is in contact with the semiconductor film,

wherein a thickness of the first gate electrode is selected so that a channel length is three times or more as long as an apparent channel length which is a distance between the pair of electrodes when seen from above.

7. The method for manufacturing a semiconductor device, according to claim 6,

wherein the pair of electrodes is formed over the semiconductor film.

8. The method for manufacturing a semiconductor device, according to claim 6,

wherein an oxide semiconductor film is formed as the semiconductor film.

9. The method for manufacturing a semiconductor device, according to claim 6,

wherein a plasma treatment is performed on at least one of the pair of electrodes, the first gate electrode and the second gate electrode.

10. The method for manufacturing a semiconductor device, according to claim 9,

wherein the plasma treatment is a reverse sputtering treatment.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming a structure comprising an insulating surface;

forming a semiconductor film over the structure;

forming a pair of electrodes over the insulating surface so that the pair of electrodes does not overlap with a gate electrode and is in contact with the semiconductor film;

forming a gate insulating film over the structure; and

forming the gate electrode over the gate insulating film,

wherein a thickness of the structure is selected so that a channel length is three times or more as long as an apparent channel length which is a distance between the pair of electrodes when seen from above.

12. The method for manufacturing a semiconductor device, according to claim 11,

wherein the pair of electrodes is formed over the semiconductor film.

13. The method for manufacturing a semiconductor device, according to claim 11,

wherein an oxide semiconductor film is formed as the semiconductor film.

14. The method for manufacturing a semiconductor device, according to claim 11,

wherein a plasma treatment is performed on at least one of the pair of electrodes, the structure and the gate electrode.

15. The method for manufacturing a semiconductor device, according to claim 14,

wherein the plasma treatment is a reverse sputtering treatment.