Array substrate including thin film transistor and method of fabricating the same

• US 8,710,497 B2
• Filed: 12/08/2011
• Issued: 04/29/2014
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Inpria Corporation, LG Display Co., Ltd.
• Original Assignee: Inpria Corporation, LG Display Co., Ltd.
• Inventors: Kim, Jung Han, Jiang, Kai, Kim, Chi-Wan, Anderson, Jeremy T.
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US13/315,049
• Publication Number:
  US 20130146862A1
• Time in Patent Office: 873 Days
• Field of Search: 257/43, 257/223, 257/227, 257/291, 257/292, 257/439, 257/443, 257/655, 257/E27.1, 257/E27.125, 257/E27.112, 257/E29.117, 257/E29.145, 257/E29.147, 257/E29.151, 257/E29.182, 257/E29.202, 257E29273-E29299, 257/E29.314, 257/E29.32, 257/E23.016, 257/E21.094, 257/E21.104, 257/E21.121, 257/E21.372, 257E21411-E21416, 257252-254, 257257-258, 438/149, 438/22, 438/24, 438/48
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An array substrate includes: a substrate; a gate line and a gate electrode on the substrate; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including a first insulator and a second insulator on the first insulator, wherein the first insulator includes an aluminum oxide material and has a first thickness, and the second insulator includes a hafnium oxide material and has a second thickness; an oxide semiconductor layer on the gate insulating layer over the gate electrode; a data line over the gate insulating layer; a source electrode and a drain electrode contacting the oxide semiconductor layer; a passivation layer on the data line, the source electrode and the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to a drain electrode through a drain contact hole.

Claims

1. An array substrate, comprising:

a substrate;

a gate electrode on the substrate;

a gate insulating layer on the gate electrode, the gate insulating layer including a first insulator and a second insulator on the first insulator, wherein the first insulator includes an aluminum oxide material and has a first thickness, and the second insulator includes a hafnium oxide material and has a second thickness;

an oxide semiconductor layer on the gate insulating layer over the gate electrode;

a source electrode and a drain electrode contacting the oxide semiconductor layer, the source electrode and the drain electrode spaced apart from each other;

a passivation layer on the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and

a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole,

wherein the aluminum oxide material includes a phosphate (PO₄³⁻

) to be expressed as Al₂(PO₄)_2-xO_3x/2(0≦

x≦

1.5).

2. The array substrate according to claim 1, wherein the source and drain electrodes are formed on the oxide semiconductor layer such that a top surface of the oxide semiconductor layer contacts bottom surfaces of the source and drain electrodes.

3. The array substrate according to claim 2, further comprising an etch stopper formed on the oxide semiconductor layer and formed between the source and drain electrodes, the etch stopper including an insulating material and disposed on a central portion of the oxide semiconductor layer.

4. The array substrate according to claim 1, wherein the oxide semiconductor layer is formed on the source and drain electrodes such that a bottom surface of the oxide semiconductor layer contacts top surfaces of the source and drain electrodes.

5. The array substrate according to claim 1, wherein the gate insulating layer has a capacitance density within a range of about 10 nF/cm² to about 30 nF/cm², the first insulator has a dielectric constant within a range of about 4 to about 6, and the second insulator has a dielectric constant within a range of about 9 to about 12.

6. The array substrate according to claim 1, wherein the hafnium oxide material includes a sulfate (SO₄²⁻

) to be expressed as HfO_2-x(SO₄)_x(0.2≦

x≦

1).

7. The array substrate according to claim 1, wherein the first thickness is within a range of about 100 nm to about 400 nm, and the second thickness is within a range of about 10 nm to about 70 nm.

8. The array substrate according to claim 1, wherein the oxide semiconductor layer includes a zinc oxide material.

9. The array substrate according to claim 8, wherein the zinc oxide material includes at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO) and zinc indium oxide (ZIO).

10. A method of fabricating an array substrate, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode, the gate insulating layer including a first insulator and a second insulator on the first insulator, wherein the first insulator includes an aluminum oxide material and has a first thickness, and the second insulator includes a hafnium oxide material and has a second thickness;

forming an oxide semiconductor layer on the gate insulating layer over the gate electrode;

forming a source electrode and a drain electrode over the gate insulating layer, the source electrode and the drain electrode contacting the oxide semiconductor layer and spaced apart from each other;

forming a passivation layer on the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and

forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole,

wherein the aluminum oxide material includes a phosphate (PO₄³⁻

) to be expressed as Al₂(PO₄)_2-xO_3x/2(0≦

x≦

1.5).

11. The method according to claim 10, wherein the source and drain electrodes are formed on the oxide semiconductor layer such that a top surface of the oxide semiconductor layer contacts bottom surfaces of the source and drain electrodes.

12. The method according to claim 11, further comprising forming an etch stopper formed on the oxide semiconductor layer and formed between the source and drain electrodes, the etch stopper including an insulating material and disposed on a central portion of the oxide semiconductor layer.

13. The method according to claim 10, wherein the oxide semiconductor layer is formed on the source and drain electrodes such that a bottom surface of the oxide semiconductor layer contacts top surfaces of the source and drain electrodes.

14. The method according to claim 10, wherein the hafnium oxide material includes a sulfate (SO₄²⁻

) to be expressed as HfO_2-x(SO₄)_x(0.2≦

x≦

1).

15. The method according to claim 10, wherein the first thickness is within a range of about 100 nm to about 400nm, and the second thickness is within a range of about 10 nm to about 70 nm.

16. The method according to claim 10, wherein forming the gate insulating layer comprises:

forming an aluminum oxide material layer on the gate electrode by coating a first solution including the aluminum oxide material and a first solvent;

forming a hafnium oxide material layer on the aluminum oxide material layer by coating a second solution including the hafnium oxide material and a second solvent; and

removing the first and second solvents from the aluminum oxide material layer and the hafnium oxide material layer by disposing the substrate having the aluminum oxide material layer and the hafnium oxide material layer in a first hardening apparatus at a temperature within a range of about 300°

C. to about 350°

C. for a first time period.

17. The method according to claim 16, wherein the first time period is within a range of about 5 minutes to about 120 minutes.

18. The method according to claim 16, wherein each of the aluminum oxide material layer and the hafnium oxide material layer are formed using one of a spin coating apparatus, a slot coating apparatus, an inkjet printing apparatus, and a mist coating apparatus.

19. The method according to claim 16, wherein forming the gate insulating layer further comprises:

removing the first solvent from the aluminum oxide material layer by disposing the substrate having the aluminum oxide material layer in a first drying apparatus at a temperature within a range of about 240°

C. to about 300°

C.; and

removing the second solvent from the hafnium oxide material layer by disposing the substrate having the hafnium oxide material layer in a second drying apparatus at a temperature within a range of about 240°

C. to about 300°

C.

20. The method according to claim 10, wherein the oxide semiconductor layer includes a zinc oxide material.

21. The method according to claim 20, wherein the zinc oxide material includes at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO) and zinc indium oxide (ZIO).

22. The method according to claim 10, wherein forming the oxide semiconductor layer comprises:

forming an oxide semiconductor material layer on the gate insulating layer by coating a solution including an oxide semiconductor material and a solvent using one of a spin coating apparatus, a slot coating apparatus, an inkjet printing apparatus and a mist coating apparatus;

removing the solvent from the oxide semiconductor material layer by disposing the substrate having the oxide semiconductor material layer in a drying apparatus at a temperature within a range of about 240°

C. to about 300°

C.; and

removing the solvent from the oxide semiconductor material layer by disposing the substrate having the oxide semiconductor material layer in a hardening apparatus at a temperature within a range of about 300°

C. to about 350°

C. for about 5 minutes to about 120 minutes.