High power insulated gate bipolar transistors

• US 8,710,510 B2
• Filed: 06/18/2007
• Issued: 04/29/2014
• Est. Priority Date: 08/17/2006
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Ryu, Sei-Hyung, Jonas, Charlotte, Agarwal, Anant K.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US11/764,492
• Publication Number:
  US 20080105949A1
• Time in Patent Office: 2,507 Days
• Field of Search: 257/77, 257/237, 257/287, 257/E29.197, 257/E29.201, 257/E21.382, 257/E27.148, 257/E29.265, 257/E29.314, 257/E21.421, 257/E21.054, 257/E21.065, 438/68, 438/112, 438/430, 438/931
• US Class Current: 257/77
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

Claims

1. A transistor, comprising:

a drift layer having a first conductivity type;

a heavily doped well region in the drift layer and having a second conductivity type opposite the first conductivity type;

an epitaxial channel adjustment layer on the drift layer and having the first conductivity type;

an emitter region adjacent the epitaxial channel adjustment layer and extending through the epitaxial channel adjustment layer and into the well region, the emitter region having the first conductivity type and at least partially defining a channel region in the well region adjacent to the emitter region;

a gate oxide layer on the channel region; and

a gate on the gate oxide layer;

wherein the drift layer comprises a JFET region adjacent to the well region, and wherein the emitter region is spaced apart from the JFET region and defines the channel region between the emitter region and the JFET region, and wherein the JFET region has a higher dopant concentration than a remaining portion of the drift layer.

2. The transistor of claim 1, wherein the second conductivity type is n-type and the first conductivity type is p-type.

3. The transistor of claim 1, further comprising:

a connector region of the second conductivity type extending from a surface of the epitaxial channel adjustment layer into the well region, wherein the connector region is formed by selective implantation of second conductivity type dopants such that a distance from a bottom of the connector region to a bottom of the well region is substantially equal to a distance from a bottom of the emitter region to the bottom of the well region;

a first ohmic contact on the connector region;

a second ohmic contact on the emitter region and comprising a material different from the first ohmic contact; and

a metal overlayer electrically connecting the first ohmic contact and the second ohmic contact.

4. The transistor of claim 3, wherein the first ohmic contact comprises a nickel-based conductive material and wherein the second ohmic contact comprises an aluminum-based conductive material.

5. The transistor of claim 1, wherein the epitaxial channel adjustment layer has a thickness of about 0.25 μ

m or more.

6. The transistor of claim 1, wherein a distance from a bottom of the emitter region to a bottom of the well region is about 0.45 μ

m or more.

7. The transistor of claim 1, wherein the epitaxial channel adjustment layer has a thickness of about 0.1 μ

m to about 0.5 μ

m and a net doping concentration of about 1×

10¹⁶ cm <sup>−

3</sup> to about 5×

10¹⁸ cm<sup>−

3</sup>.

8. The transistor of claim 1, further comprising a silicon carbide substrate wherein the drift layer comprises a silicon carbide epitaxial layer on the substrate.

9. A transistor, comprising:

a p-type drift layer;

an n+-type well in the drift layer;

a p-type epitaxial channel adjustment layer on the drift layer;

a p-type emitter region extending through the epitaxial channel adjustment layer and into the n+-type well, the p-type emitter region at least partially defining a channel region in the n+-type well adjacent the p-type emitter region;

an n-type connector region extending through the epitaxial channel adjustment layer and into the n+-type well, wherein the n-type connector region is formed by selective implantation of n-type dopants such that a distance from a bottom of the connector region to a bottom of the well is substantially equal to a distance from a bottom of the emitter region to the bottom of the well;

a first ohmic contact including aluminum on the p-type emitter region;

a second ohmic contact including nickel on the n-type connector region;

a gate oxide layer on the channel region;

a gate on the gate oxide layer;

an interlayer dielectric layer on the gate, the interlayer dielectric layer including a first opening exposing the first ohmic contact and a second opening exposing the second ohmic contact; and

a metal overlayer on the interlayer dielectric layer and electrically connecting the first ohmic contact and the second ohmic contact;

wherein the drift layer comprises a JFET region adjacent to the well and wherein the emitter region is spaced apart from the JFET region and defines the channel region between the emitter region and the JFET region, and wherein the JFET region has a higher dopant concentration than a remaining portion of the drift layer.

10. A transistor, comprising:

a p-type drift layer;

an n+-type well region in the drift layer;

a p-type epitaxial channel adjustment layer on the drift layer and having the first conductivity type, the p-type epitaxial channel adjustment layer extending across the n+-type well region;

a p-type emitter region adjacent the p-type epitaxial channel adjustment layer and extending through the p-type epitaxial channel adjustment layer and into the well region, the emitter region at least partially defining a channel region in the well region adjacent to the emitter region;

a gate insulation layer on the channel region; and

a gate on the gate insulation layer;

wherein the drift layer comprises a JFET region adjacent to the well region, and wherein the emitter region is spaced apart from the JFET region and defines the channel region between the emitter region and the JFET region, and wherein the JFET region has a higher dopant concentration than a remaining portion of the drift layer.

11. The transistor of claim 10, further comprising:

a connector region of the second conductivity type extending from a surface of the epitaxial channel adjustment layer into the well region, wherein the connector region is formed by selective implantation of second conductivity type dopants such that a distance from a bottom of the connector region to a bottom of the well region is substantially equal to a distance from a bottom of the emitter region to the bottom of the well region;

a first ohmic contact on the connector region;

a second ohmic contact on the emitter region and comprising a material different from the first ohmic contact; and

a metal overlayer electrically connecting the first ohmic contact and the second ohmic contact.

12. The transistor of claim 10, wherein the epitaxial channel adjustment layer has a thickness of about 0.25 μ

m or more.

13. The transistor of claim 10, wherein a distance from a bottom of the emitter region to a bottom of the well region is about 0.45 μ

m or more.

14. The transistor of claim 10, wherein the eitaxial channel adjustment layer has a thickness of about 0.1 μ

m to about 0.5 μ

m and a net doping concentration of about 1×

10¹⁶ cm<sup>−

3</sup> to about 5×

10<sup>18 −

3</sup> .

15. The transistor of claim 10, further comprising a silicon carbide substrate wherein the drift layer comprises a silicon carbide epitaxial layer on the substrate.