Micromachined devices and fabricating the same

• US 8,710,599 B2
• Filed: 08/03/2010
• Issued: 04/29/2014
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marx, David Lambe, Acar, Cenk, Bryzek, Janusz, Akkaraju, Sandeep
• Primary Examiner(s): Quach, Tuan N
• Application Number:
  US12/849,787
• Publication Number:
  US 20110031565A1
• Time in Patent Office: 1,365 Days
• Field of Search: 257/417, 257/E21.499, 257/E29.324, 438/51
• US Class Current: 257/417
• CPC Class Codes: G01C 19/5712 the devices involving a micromechanical structure
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01P 2015/082 for two degrees of freedom of movement of a single mass
• CPC Class Codes: G01P 2015/0842 the mass being of clover leaf shape
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer.

Claims

1. A device, comprising:

a first wafer having at least one via; and

a second wafer bonded to the first wafer and having a micro-electromechanical-systems (MEMS) layer,

wherein the via forms a closed loop when viewed in a direction normal to a top surface of the first wafer to thereby define a first conductive region of the first wafer electrically isolated from the remainder of the first wafer.

2. A device of claim 1, wherein the MEMS layer is adapted to measure one or more of angular rates about three axes and linear accelerations about the three axes.

3. A device as recited in claim 1, wherein the first wafer includes a dielectric layer formed on a surface thereof and one or more contacts disposed over the dielectric layer, one of the contacts being electrically connected to the first conductive region.

4. A device as recited in claim 1, wherein the via includes a core filled with an electrically conducting material and a dielectric layer surrounding the core.

5. A device as recited in claim 4, wherein the first wafer includes a dielectric layer formed on a surface thereof and one or more contacts disposed over the dielectric layer, one of the contacts being electrically connected to the core of the via.

6. A device as recited in claim 1, wherein the first wafer includes first and second vias, the first via forming a first closed loop to define a first conductive region, the second via forming a second closed loop surrounding the first closed loop to thereby define a second conductive region having a ring shape and electrically insulated from the first conductive region.

7. A device as recited in claim 6, wherein the first and second conductive regions are respectively connected to first and second contacts, the first conductive region being adapted to operate as a sensor and communicate a signal via the first contact, the second conductive region being connected to a ground via the second contact.

8. A device as recited in claim 1, further comprising:

a third wafer bonded to the first and second wafers.

9. A device as recited in claim 8, further comprising:

an ASIC wafer bonded to the first wafer.

10. A device as recited in claim 1, wherein at least one of the first and second wafers includes a cavity to thereby cause portions of the first wafer to be spaced apart from the second wafer.