Method for testing multi-chip stacked packages

• US 8,710,859 B2
• Filed: 09/23/2011
• Issued: 04/29/2014
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Chang, Kai-Jun
• Primary Examiner(s): Phan, Huy
• Assistant Examiner(s): SPLIT, JAMES G
• Application Number:
  US13/242,400
• Publication Number:
  US 20130076384A1
• Time in Patent Office: 949 Days
• Field of Search: 324/756.01, 324/756.02, 324/757.01, 324/757.04, 324/757.05, 32476201-76206, 324/754.01, 438/10, 438/17, 438106-114, 438/118, 438/55, 438/15, 257/777, 257/E21.521, 257/E21.525, 257/E25.013
• US Class Current: 324/756.01
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls

Abstract

Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV'"'"'s where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Claims

1. A method for testing a plurality of multi-chip stacked packages, comprising:

providing one or more substrate-less chip cubes each consisting of a plurality of vertically stacked chips, wherein a stacked gap is formed between two adjacent chips and a plurality of testing electrodes are disposed on a top chip surface of each substrate-less chip cube;

attaching the substrate-less chip cubes onto an adhesive tape with the testing electrodes away from the adhesive tape, wherein the adhesive tape is attached inside an opening of a tape carrier, wherein the tape carrier is a strip;

forming a filling encapsulant on the adhesive tape to fully fill the stacked gaps between the stacked chips;

fixing the tape carrier on a wafer testing carrier to allow the substrate-less chip cubes being loaded into a wafer tester without releasing from the adhesive tape;

wherein the wafer testing carrier has a disc-shaped major body made of a hard material to provide a placing surface larger than the adhesive tape, and the adhesive tape is completely attached onto the placing surface so that the substrate-less chip cubes are supported on the wafer testing carrier; and

probing the testing electrodes of the substrate-less chip cubes by a plurality of testing probes inside a wafer tester to electrically test the substrate-less chip cubes.

2. The method as claimed in claim 1, further comprising a step of releasing the tape carrier from the wafer testing carrier after the probing step.

3. The method as claimed in claim 1, wherein the wafer testing carrier is larger than the tape carrier where both have different shapes.

4. The method as claimed in claim 1, wherein the wafer testing carrier has a plurality of fixing kits disposed on the major body to fix the tape carrier.

5. The method as claimed in claim 4, wherein the fixing kits fix a plurality of corners of the tape carrier when the tape carrier is fixed.

6. The method as claimed in claim 1, wafer testing carrier further has a fitting window sunk from the placing surface, wherein the shape of the fitting window matches to the shape of the tape carrier.

7. The method as claimed in claim 1, wherein the step of forming the filling encapsulant includes a de-bleeding step of removing a bleeding portion of the filling encapsulant exceeding the footprints of the substrate-less chip cubes.

8. The method as claimed in claim 7, wherein the filling encapsulant encapsulates a plurality of sidewalls of the chips after the de-bleeding step.

9. The method as claimed in claim 1, wherein each chip has a plurality of through silicon vias disposed inside, wherein a plurality of interconnecting electrodes are disposed in the stacked gaps between the stacked chips of the substrate-less chip cubes to electrically connect the through silicon vias.