Resonant oscillator with start up and shut down circuitry

• US 8,710,936 B2
• Filed: 12/08/2011
• Issued: 04/29/2014
• Est. Priority Date: 08/05/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chou, Catherine S., Athas, William C., Sullens, Heather R.
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US13/314,825
• Publication Number:
  US 20120105162A1
• Time in Patent Office: 873 Days
• Field of Search: 331/117.FE, 331/185
• US Class Current: 331/117.FE
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03B 5/06 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A system which starts up and shuts down a resonant oscillator circuit. During start up, the system operates a driving circuit, which is external to the resonant oscillator circuit, wherein the driving circuit uses a first clock signal to control a first phase output of the resonant oscillator circuit. At the same time, the driving circuit uses a second clock signal to control a second phase output of the resonant oscillator circuit, wherein the first and second clock signals have opposite phases. While the first and second phase outputs are being controlled, the system ramps up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods. During shut down, the system shuts down the resonant oscillator circuit by ramping down the input voltage. Next, the system clamps the first and second phase outputs to a fixed voltage.

Claims

1. A method for starting up a resonant oscillator circuit, the method comprising:

operating a driving circuit, which is external to the resonant oscillator circuit, wherein the driving circuit uses a first clock signal to control a first phase output of the resonant oscillator circuit, and uses a second clock signal to control a second phase output of the resonant oscillator circuit, wherein the first and second clock signals have opposite phases;

while the first and second phase outputs are being controlled, ramping up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods; and

discontinuing the controlling of the first and second phase outputs after the multiple initial oscillation periods complete.

2. The method of claim 1, wherein using the first and second clock signals to control the first and second phase outputs involves driving the first clock signal onto a first N-FET gate which clamps the output of the resonant oscillator circuit to a desired frequency, and driving the second clock signal onto a second N-FET gate which clamps the output of the resonant oscillator circuit to the desired frequency.

3. The method of claim 1, wherein the driving circuit includes a programmable microcontroller.

4. The method of claim 1, wherein ramping up the input voltage involves using an RC filter to ramp up the input voltage at a controlled rate.

5. The method of claim 1, further comprising shutting down the resonant oscillator circuit by:

ramping down the input voltage; and

after the input voltage has been ramped down, clamping the first and second phase outputs to a fixed voltage.

6. The method of claim 5, wherein ramping down the input voltage involves:

disconnecting a power source from the input voltage; and

draining charge from a capacitor having a first terminal coupled to the input voltage and a second terminal coupled to a base voltage, wherein draining the charge involves coupling the first terminal of the capacitor to the base voltage through a resistor.

7. The system of claim 1, wherein the resonant oscillator circuit is an LC oscillator circuit which includes at least two inductors and at least two capacitances.

8. The method of claim 7, wherein the resonant oscillator circuit comprises:

the first phase output;

the second phase output;

a first inductor with a first terminal coupled to an input voltage and a second terminal coupled to the first phase output;

a second inductor with a first terminal coupled to the input voltage and a second terminal coupled to the second phase output;

a first N-type transistor with a source terminal coupled to a base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output; and

a second N-type transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output.

9. The method of claim 8,

wherein the resonant oscillator circuit additionally comprises a first capacitance and a second capacitance, which operate in concert with the first inductor and the second inductor to produce resonant oscillations;

wherein the first capacitance includes capacitive components from a load on the first phase output and the gate terminal of the second N-type transistor; and

wherein the second capacitance includes capacitive components from a load on the second phase output and the gate terminal of the first N-type transistor.

10. A resonant oscillator circuit, comprising:

a first phase output;

a second phase output;

a first inductor;

a second inductor;

a first capacitance;

a second capacitance;

wherein the first and second inductors are configured to operate with the first and second capacitances to produce resonant oscillations which appear at the first phase output and the second phase output;

a driving circuit configured to use a first clock signal to control the first phase output, and to use a second clock signal to control the second phase output, wherein the first and second clock signals have opposite phases;

wherein the driving circuit is configured to discontinue the controlling of the first and second phase outputs after the multiple initial oscillation periods complete; and

a ramping circuit configured to ramp up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods.

11. The resonant oscillator circuit of claim 10, wherein while using the first and second clock signals to control the first and second phase outputs, the driving circuit is configured to drive the first clock signal onto a first N-FET gate which clamps the output of the resonant oscillator circuit to a desired frequency, and to drive the second clock signal onto a second N-FET gate which clamps the output of the resonant oscillator circuit to the desired frequency.

12. The resonant oscillator circuit of claim 10, wherein the driving circuit includes a programmable microcontroller.

13. The resonant oscillator circuit of claim 10, wherein the ramping circuit includes an RC filter to facilitate ramping up the input voltage at a controlled rate.

14. The resonant oscillator circuit of claim 10,

wherein during an oscillator-shut-down operation, the ramping circuit is configured to ramp down the input voltage;

and

wherein after the input voltage has been ramped down for a period of time, the driving circuit is configured to clamp the first and second phase outputs to a fixed voltage.

15. The resonant oscillator circuit of claim 14, wherein while ramping down the input voltage, the ramping circuit is configured to:

disconnect a power source from the input voltage; and

drain charge from a capacitor having a first terminal coupled to the input voltage and a second terminal coupled to a base voltage, wherein draining the charge involves coupling the first terminal of the capacitor to the base voltage through a resistor.

16. The resonant oscillator circuit of claim 10,

wherein the first inductor includes a first terminal coupled to the input voltage and a second terminal coupled to the first phase output;

wherein the second inductor includes a first terminal coupled to the input voltage and a second terminal coupled to the second phase output;

wherein the resonant oscillator circuit also includes a first N-type transistor with a source terminal coupled to a base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output;

wherein the resonant oscillator circuit additionally includes a second N-type transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output;

wherein the first capacitance includes capacitive components from a load on the first phase output and the gate terminal of the second N-type transistor; and

wherein the second capacitance includes capacitive components from a load on the second phase output and the gate terminal of the first N-type transistor.

17. The resonant oscillator circuit of claim 10,

wherein the first phase output is coupled to a first bootstrapping circuit which adds one or more voltage offsets to the first phase output to produce one or more boosted first phase outputs;

and

wherein the second phase output is coupled to a second bootstrapping circuit which adds one or more voltage offsets to the second phase output to produce one or more boosted second phase outputs.

18. A resonant oscillator circuit, comprising:

a resonant oscillator with a first phase output and a second phase output, which produce clock signals with substantially opposite clock phases; and

a start up circuit for the resonant oscillator which includes,

a ramping circuit configured to ramp up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods; and

a driving circuit, wherein during the multiple initial oscillation periods, the driving circuit is configured to use a first clock signal to control the first phase output, and a second clock signal to control the second phase output, wherein the first and second clock signals have opposite phases;

wherein the driving circuit is configured to discontinue the controlling of the first and second phase outputs after the multiple initial oscillation periods complete.

19. The resonant oscillator circuit of claim 18, wherein while using the first and second clock signals to control the first and second phase outputs, the driving circuit is configured to drive the first clock signal onto a first N-FET gate which clamps the output of the resonant oscillator circuit to a desired frequency, and to drive the second clock signal onto a second N-FET gate which clamps the output of the resonant oscillator circuit to the desired frequency.

20. The resonant oscillator circuit of claim 18,

wherein during an oscillator-shut-down operation, the ramping circuit is configured to ramp down the input voltage;

and

wherein after the input voltage has been ramped down, the driving circuit is configured to clamp the first and second phase outputs to a fixed voltage.

21. The resonant oscillator circuit of claim 20, wherein while ramping down the input voltage, the ramping circuit is configured to:

disconnect a power source from the input voltage; and

drain charge from a capacitor having a first terminal coupled to the input voltage and a second terminal coupled to a base voltage, wherein draining the charge involves coupling the first terminal of the capacitor to the base voltage through a resistor.

22. The resonant oscillator circuit of claim 18, wherein the resonant oscillator circuit further comprises:

a first inductor;

a second inductor;

a first capacitance; and

a second capacitance;

wherein the first and second inductors are configured to operate with the first and second capacitances to produce resonant oscillations which appear at the first phase output and the second phase output.