Functional component compensation reconfiguration system and method

• US 8,711,161 B1
• Filed: 06/21/2006
• Issued: 04/29/2014
• Est. Priority Date: 12/18/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Young, Charles Chew-Yuen, Tamasi, Anthony M., Van Dyke, James M., Montrym, John S., Scotzniovsky, Stefan, Cory, Bruce, Treicher, Sean J.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US11/472,865
• Time in Patent Office: 2,869 Days
• Field of Search: 345/530, 345/531, 345/555, 345/568, 345/501, 345/502, 345/519, 345/421, 345/422
• US Class Current: 345/531
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/1428 with loss of hardware functionality
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

Claims

1. A configurable memory system comprising:

a plurality of memory cells for storing information;

a bus for communicating information to and from said plurality of memory cells; and

a memory cell configuration controller for selectively configuring said memory cells, wherein a size of a memory word is correspondingly selectively changed in accordance with said configuring, wherein said memory cell configuration controller provides configuration information and memory word size information to other components that adjust their operations accordingly, including adjusting to prevent overflow.

2. A configurable memory system of claim 1 wherein said other components include a memory controller.

3. A configurable memory system of claim 1 wherein said other components include a processor.

4. A configurable memory system of claim 1 wherein said memory cell configuration controller performs said memory cell configuration on a memory cell group basis.

5. A configurable memory system of claim 1 wherein said memory cell configuration controller performs said memory cell configuration on a word line basis.

6. A configurable memory system of claim 1 wherein said memory cell configuration controller performs said memory cell configuration on memory cell block basis.

7. A configuration method comprising:

configuring a plurality of said memory, wherein a size of a memory word is correspondingly changed in accordance with said configuring; and

forwarding configuration information and memory word size information to another component that adjust its operations accordingly, including adjusting to prevent overflow.

8. A configuration method of claim 7 wherein said configuring includes adjusting addresses of said memory cells.

9. A configuration method of claim 7 wherein said configuring includes incrementing addresses above a disabled subset of said plurality of memory cells internally so that memory space appears continuous to external components.

10. A configuration method of claim 7 wherein said configuring includes adjusting addresses of said memory cells associated with a particular function.

11. A configuration method of claim 7 wherein said configuring includes adjusting addresses of said memory cells associated with a compression tag function.

12. A configuration method of claim 7 wherein said configuring includes adjusting addresses of said memory cells associated with a depth culling function.

13. A configuration method of claim 7 further comprising adjusting operations in other components based upon said forwarded configuration information.

14. A configuration method of claim 13 wherein said adjusting includes reducing presentation regions associated with compression operations to prevent overflow.

15. A configuration method of claim 13 wherein said adjusting includes alter depth culling operations to prevent overflow of memory associated with depth culling operations.

16. A configurable system comprising:

a processing core for processing information;

a memory for storing said information;

wherein said memory is selectively configured and wherein a size of a memory word is correspondingly selectively changed in accordance with said configuring, wherein configuration information and memory word size information is provided to other components that adjust their operations accordingly, including said processing core that adjusts operations accordingly, including adjusting to prevent overflow.

17. A configurable system of claim 16 wherein said memory is configured on a word line basis and said configuring includes adjusting physical memory addresses to maintain a sequential addressing scheme of enabled storage components within said memory.

18. A configurable system of claim 16 wherein said configuring includes adjusting logical addresses in a virtual addressing scheme associated with said memory.

19. A configurable system of claim 16 wherein said configuring includes incrementing addresses around a disabled subset of memory components internally so that memory space appears continuous to said processor.

20. A configurable system of claim 16 wherein said processor is a graphics processor and said memory is a graphics buffer.