Memory cell and memory cell array using the same

• US 8,711,598 B1
• Filed: 11/21/2012
• Issued: 04/29/2014
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Shih-Chin, Chen, Hsin-Wen, Shuai, Chi-Chang
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): ISLAM, MUHAMMAD S
• Application Number:
  US13/682,742
• Publication Number:
  US 20140140120A1
• Time in Patent Office: 524 Days
• Field of Search: 365/72, 365/154, 365/222, 365/203, 365/189
• US Class Current: 365/72
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Claims

1. A memory cell, comprising:

a first P-type transistor configured to have a first source/drain thereof electrically coupled to a first voltage;

a second P-type transistor configured to have a first source/drain thereof electrically coupled to the first voltage;

a first N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the first P-type transistor, a second source/drain thereof electrically coupled to a second voltage, and a gate thereof electrically coupled to the gate of the first P-type transistor;

a second N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to the gate of the second P-type transistor;

a third N-type transistor configured to have a first source/drain thereof electrically coupled to a write word line, a second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to a first write bit line; and

a fourth N-type transistor configured to have a first source/drain thereof electrically coupled to the write word line, a second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and a gate thereof electrically coupled to a second write bit line.

2. The memory cell according to claim 1, further comprising:

a fifth N-type transistor configured to have a first source/drain thereof electrically coupled to a read bit line, and a gate thereof electrically coupled to a read word line; and

a sixth N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the fifth N-type transistor, the second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to the gate of the first N-type transistor.

3. The memory cell according to claim 1, wherein the first voltage is configured to have a value greater than that of the second voltage.

4. The memory cell according to claim 1, wherein the first write bit line is configured to turn on or turn off the third N-type transistor, the second write bit line is configured to turn on or turn off the fourth N-type transistor.

5. The memory cell according to claim 4, wherein the third and fourth N-type transistors are controlled to be turned on at different times.

6. The memory cell according to claim 4, wherein the write word line is configured to have a low voltage level thereon when the first write bit line has a high voltage level thereon and the second write bit line has a low voltage level thereon.

7. The memory cell according to claim 4, wherein the write word line is configured to have a low voltage level thereon when the first write bit line has a low voltage level thereon and the second write bit line has a high voltage level thereon.

8. The memory cell according to claim 1, wherein each of the third and the fourth N-type transistors is replaced by a P-type transistor.

9. A memory cell array, comprising:

a plurality of write word lines;

a plurality of first write bit lines;

a plurality of second write bit lines; and

a plurality of memory cells arranged in a matrix form, each one of the memory cells being electrically coupled to one of the write word lines, one of the first write bit lines and one of the second write bit lines, each one of the memory cells comprising;

a first P-type transistor configured to have a first source/drain thereof electrically coupled to a first voltage;

a second P-type transistor configured to have a first source/drain thereof electrically coupled to the first voltage;

a first N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the first P-type transistor, a second source/drain thereof electrically coupled to a second voltage, and a gate thereof electrically coupled to a gate of the first P-type transistor;

a second N-type transistor configured to have a first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, a second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to a gate of the second P-type transistor;

a third N-type transistor configured to have a first source/drain thereof electrically coupled to one of the write word lines, a second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and a gate thereof electrically coupled to one of the first write bit lines; and

a fourth N-type transistor configured to have a first source/drain thereof electrically coupled to one of the write word lines, a second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and a gate thereof electrically coupled to one of the second write bit lines.

10. The memory cell array according to claim 9, wherein each one of the memory cells further comprises:

a fifth N-type transistor configured to have a first source/drain thereof electrically coupled to one of the read bit lines, and a gate thereof electrically coupled to one of the read word lines; and

a sixth N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the fifth N-type transistor, the second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to the gate of the first N-type transistor.

11. The memory cell array according to claim 9, wherein the first voltage is configured to have a value greater than that of the second voltage.

12. The memory cell array according to claim 9, wherein one of the first write bit lines is configured to turn on or turn off the third N-type transistor, one of the second write bit lines is configured to turn on or turn off the fourth N-type transistor.

13. The memory cell array according to claim 12, wherein the third and fourth N-type transistors are controlled to be turned on at different times.

14. The memory cell array according to claim 12, wherein one of the write word lines is configured to have a low voltage level thereon when one of the first write bit lines has a high voltage level thereon and one of the second write bit lines has a low voltage level thereon.

15. The memory cell array according to claim 12, wherein one of the write word lines is configured to have a low voltage level thereon when one of the first write bit lines has a low voltage level thereon and one of the second write bit lines has a high voltage level thereon.

16. The memory cell array according to claim 9, wherein each of the third and the fourth N-type transistors is replaced by a P-type transistor.