Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 8,711,622 B2
• Filed: 07/12/2013
• Issued: 04/29/2014
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/941,227
• Publication Number:
  US 20130301349A1
• Time in Patent Office: 291 Days
• Field of Search: 365/185.05, 365/185.17, 365/182
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein to define a state of said memory cell; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said memory cell.

2. The semiconductor memory device of claim 1, wherein said at least two memory cells each further comprise first and second conductive regions interfacing with said floating body region.

3. The semiconductor memory device of claim 2, wherein said at least two memory cells each further comprise a gate region positioned between said first and second conductive regions.

4. The semiconductor memory device of claim 2, wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, said first conductive region, said second conductive region, and said back-bias region have a second conductivity type selected from p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

5. The semiconductor memory device of claim 4, wherein said at least two memory cells each further comprise a substrate having a first conductivity type selected from p-type and n-type conductivity types.

6. The semiconductor memory device of claim 1, wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, applications of voltage to said back-bias region maintains said first memory cell in said first state and said second memory cell in said second state.

7. The semiconductor memory device of claim 6, wherein said first state is different from said second state.

8. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region;

wherein said back-bias region is configured to establish at least two different stable floating body charge levels by application of voltage to said back-bias region.

9. The semiconductor memory device of claim 8, wherein said voltage applied to said back-bias region is a constant positive voltage bias.

10. The semiconductor memory device of claim 8, wherein said voltage applied to said back-bias region is a periodic pulse of positive voltage.

11. The semiconductor memory device of claim 8, wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, applications of voltage to said back-bias region maintains said first memory cell in said first state and said second memory cell in said second state.

12. The semiconductor memory device of claim 11, wherein said first state is different from said second state.

13. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region commonly connected to said at least two of said memory cells.

14. The semiconductor memory device of claim 13, wherein each said floating body region has a first conductivity type selected from p-type and n-type conductivity types, each said first region, second region, and back-bias region have a second conductivity type selected from p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

15. The semiconductor memory device of claim 13, wherein said at least two memory cells each further comprise a substrate having a first conductivity type selected from p-type and n-tpye type conductivity types.

16. The semiconductor memory device of claim 13, wherein application of voltage to said back-bias region maintains current states of each said memory cell connected thereto.

17. The semiconductor memory device of claim 16, wherein said application of voltage is applied as a constant positive voltage bias.

18. The semiconductor memory device of claim 16, wherein said application of voltage is applied as a periodic pulse of positive voltage bias.

19. The semiconductor memory device of claim 13, wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, applications of voltage to said back-bias region maintains said first memory cell in said first state and said second memory cell in said second state.

20. The semiconductor memory device of claim 19, wherein said first state is different from said second state.