Memory device and semiconductor device

• US 8,711,623 B2
• Filed: 03/22/2013
• Issued: 04/29/2014
• Est. Priority Date: 03/17/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Nagatsuka, Shuhei
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/848,871
• Publication Number:
  US 20130223157A1
• Time in Patent Office: 403 Days
• Field of Search: 365/185.08, 365/189.2
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.

Claims

1. A semiconductor device comprising:

a control circuit;

a first reading circuit operationally connected to the control circuit;

a first memory portion operationally connected to the control circuit and the first reading circuit, the first memory portion including a first memory element;

a second reading circuit operationally connected to the control circuit;

a second memory portion operationally connected to the control circuit and the second reading circuit, the second memory portion including a first transistor and a second memory element; and

a comparison circuit operationally connected to the first reading circuit and the second reading circuit,

wherein the first transistor includes an oxide semiconductor in a channel formation region.

2. The semiconductor device according to claim 1,

wherein the first memory element is capable of storing first data by writing of reference data;

wherein the second memory element is capable of storing second data by writing of the reference data; and

wherein the comparison circuit is configured to compare the first data with the second data.

3. The semiconductor device according to claim 2, wherein the second memory element is capable of storing third data including a result of the comparison of the first data and the second data.

4. The semiconductor device according to claim 1 further comprising a second transistor in the second memory element.

5. The semiconductor device according to claim 4, wherein the second transistor includes an oxide semiconductor in a channel formation region.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises indium, gallium and zinc.

7. The semiconductor device according to claim 2, wherein hydrogen concentration of the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

8. The semiconductor device according to claim 2, wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

9. The semiconductor device according to claim 1, further comprising:

a first data line driver circuit operationally connected to the control circuit;

a first word line driver circuit operationally connected to the control circuit;

a second data line driver circuit operationally connected to the control circuit; and

a second word line driver circuit operationally connected to the control circuit.

10. The semiconductor device according to claim 1, wherein the first memory element is a substantially nonvolatile memory element.

11. The semiconductor device according to claim 10, wherein the first memory element comprises a third transistor which includes a floating gate between a gate electrode and an active layer.

12. A semiconductor device comprising:

a control circuit;

a first reading circuit operationally connected to the control circuit;

a first memory portion operationally connected to the control circuit and the first reading circuit, the first memory portion including a first memory element;

a second reading circuit operationally connected to the control circuit;

a second memory portion operationally connected to the control circuit and the second reading circuit, the second memory portion including a first transistor and a second memory element; and

a comparison circuit operationally connected to the first reading circuit and the second reading circuit,

wherein the first transistor includes an oxide semiconductor in a channel formation region,

wherein the first memory element includes a second transistor, and

wherein the second transistor includes silicon in a channel formation region.

13. The semiconductor device according to claim 12,

wherein the first memory element is capable of storing first data by writing of reference data;

wherein the second memory element is capable of storing second data by writing of the reference data; and

wherein the comparison circuit is configured to compare the first data with the second data.

14. The semiconductor device according to claim 13, wherein the second memory element is capable of storing third data including a result of the comparison of the first data and the second data.

15. The semiconductor device according to claim 12 further comprising a third transistor in the second memory element.

16. The semiconductor device according to claim 15, wherein the third transistor includes an oxide semiconductor in a channel formation region.

17. The semiconductor device according to claim 12, wherein the oxide semiconductor comprises indium, gallium and zinc.

18. The semiconductor device according to claim 12, wherein hydrogen concentration of the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

19. The semiconductor device according to claim 12, wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

20. The semiconductor device according to claim 12, further comprising:

a first data line driver circuit operationally connected to the control circuit;

a first word line driver circuit operationally connected to the control circuit;

a second data line driver circuit operationally connected to the control circuit; and

a second word line driver circuit operationally connected to the control circuit.

21. The semiconductor device according to claim 12, wherein the first memory element is a substantially nonvolatile memory element.

22. The semiconductor device according to claim 21, wherein the first memory element comprises a fourth transistor which includes a floating gate between a gate electrode and an active layer.