Multi-port, gigabit SERDES transceiver capable of automatic fail switchover
First Claim
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1. A transceiver, comprising:
- a first port configured to transmit and to receive data over a first plurality of lanes;
a second port configured to transmit and to receive the data over a second plurality of lanes; and
a switch selectively coupled to the first port and the second port;
wherein the switch is configured to activate the second port and to deactivate the first port when;
the data at a first lane from among the first plurality of lanes is misaligned, ora number of errors at a second lane from among the first plurality of lanes exceeds a threshold, andwherein the switch is further configured to begin its determination of whether the data at the first lane is misaligned substantially simultaneously with its determination of whether the number of errors at the second lane exceeds the threshold.
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Abstract
A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. The transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a “ring” structure around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.
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Citations
20 Claims
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1. A transceiver, comprising:
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a first port configured to transmit and to receive data over a first plurality of lanes; a second port configured to transmit and to receive the data over a second plurality of lanes; and a switch selectively coupled to the first port and the second port; wherein the switch is configured to activate the second port and to deactivate the first port when; the data at a first lane from among the first plurality of lanes is misaligned, or a number of errors at a second lane from among the first plurality of lanes exceeds a threshold, and wherein the switch is further configured to begin its determination of whether the data at the first lane is misaligned substantially simultaneously with its determination of whether the number of errors at the second lane exceeds the threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A transceiver, comprising:
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a first port configured to transmit and to receive data over a first plurality of lanes; a second port configured to transmit and to receive the data over a second plurality of lanes; and a switch selectively coupled to the first port and the second port; wherein the switch is configured to activate the second port and to deactivate the first port when; a number of errors at a first lane from among the first plurality of lanes exceeds a threshold, or the data at a second lane from among the first plurality of lanes is misaligned with the data at other lanes from among the first plurality of lanes, and wherein the switch is further configured to begin its determination of whether the number of errors at the first lane exceeds the threshold substantially simultaneously with its determination of whether the data at the second lane is misaligned with the data at the other lanes. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A transceiver, comprising:
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a first port configured to transmit and to receive data over a first plurality of lanes; a second port configured to transmit and to receive the data over a second plurality of lanes; and a switch selectively coupled to the first port and the second port; wherein the switch is configured to activate the second port and to deactivate the first port when; the data at a first lane from among the first plurality of lanes is misaligned, or the data at a second lane from among the first plurality of lanes is misaligned with the data at other lanes from among the first plurality of lanes, and wherein the switch is further configured to begin its determination of whether the data at the first lane is misaligned substantially simultaneously with its determination of whether the data at the second lane is misaligned with the data at the other lanes. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeAvago Technologies International Sales Pte Limited (Broadcom, Inc.)
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Original AssigneeBroadcom Corporation (Broadcom, Inc.)
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InventorsTran, Hoang
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Primary Examiner(s)MURPHY, RHONDA L
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Application NumberUS13/731,409Publication NumberTime in Patent Office484 DaysField of SearchNoneUS Class Current370/216CPC Class CodesG06F 13/4027 using bus bridges G06F13/40...H04B 1/38 Transceivers, i.e. devices ...
