Methods and systems for automatically identifying a logical circuit failure in a data network

• US 8,711,679 B2
• Filed: 05/15/2012
• Issued: 04/29/2014
• Est. Priority Date: 12/23/2003
• Status: Expired due to Fees

• Current Assignee: Bellsouth Intellectual Property Corporation (AT&T, Inc.)
• Original Assignee: AT&T Intellectual Property I LP (AT&T, Inc.)
• Inventors: Hollingsworth, John, Taylor, William, Massengill, David
• Primary Examiner(s): Phung, Luat
• Application Number:
  US13/472,244
• Publication Number:
  US 20120224475A1
• Time in Patent Office: 714 Days
• Field of Search: 370/242, 370/244, 370/250, 370216-219, 370/221, 370/389, 370/395.1, 714/4, 714/43
• US Class Current: 370/217
• CPC Class Codes: H04L 41/0233 Object-oriented techniques, for representation of network management data, e.g. common object request broker architecture [CORBA]
• CPC Class Codes: H04L 43/0817 by checking functioning

Abstract

A disclosed example method to identify a failure in a logical circuit involves receiving non-requested trap data from a plurality of switches forming a logical circuit. The logical circuit spans first, second, and third logical networks. The example method also involves polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit. The first switch forms a first network-to-network interface between the first logical network and the second logical network. The second switch forms a second network-to-network interface between the second logical network and the third logical network. The first and second switches are selected for polling based on the trap data indicating a problem at the first and second switches. The example method also involves identifying a failure of the logical circuit without manual intervention based on the polling.

Claims

1. A method to identify a failure in a logical circuit, the method comprising:

receiving non-requested trap data from a plurality of switches forming a logical circuit, the logical circuit spanning first, second, and third logical networks;

polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit, the first switch forming a first network-to-network interface between the first logical network and the second logical network, the second switch forming a second network-to-network interface between the second logical network and the third logical network, the first logical network being in a first local access and transport area, the second logical network being an inter-exchange carrier network, the third logical network being in a second local access and transport area, and the first and second switches selected for polling based on the trap data indicating a problem at the first and second switches; and

identifying a failure of the logical circuit without manual intervention based on the polling.

2. The method of claim 1, wherein polling the first and second switches comprises performing the polling via a network management module separate from the switches forming the logical circuit.

3. The method of claim 1, wherein polling the first and second switches comprises periodically requesting second trap data from the first and second switches.

4. The method of claim 3, wherein identifying the failure of the logical circuit comprises:

when the second trap data indicates that the at least one of the first or second network-to-network interfaces is no longer communicating data, then determining that the at least one of the first or second network-to-network interfaces has failed;

after determining that the at least one of the first or second network-to-network interfaces has failed, waiting a predetermined time period to determine whether the at least one of the first or second network-to-network interfaces is restored; and

when after the predetermined time period, the at least one of the first or second network-to-network interfaces is not restored, indicating that the logical circuit has failed.

5. The method of claim 1 further comprising:

identifying a logical identifier for the logical circuit; and

based on the logical identifier, accessing a database to identify a first logical connection associated with the first network-to-network interface and a second logical connection associated with the second network-to-network interface.

6. The method of claim 5, wherein the logical identifier is a data link connection identifier (DLCI).

7. The method of claim 5, wherein the logical identifier is a virtual path/virtual circuit identifier (VPI/VCI).

8. The method of claim 1, wherein the logical circuit is a permanent virtual circuit.

9. The method of claim 1, wherein the logical circuit is a switched virtual circuit.

10. An apparatus to automatically identify a logical circuit failure, the apparatus comprising:

a memory comprising machine readable instructions; and

a processor to execute the instructions to perform operations comprising;

analyzing non-requested trap data received from a plurality of switches forming a logical circuit, the logical circuit spanning first, second, and third logical networks;

polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit, the first switch forming a first network-to-network interface between the first logical network and the second logical network, the second switch forming a second network-to-network interface between the second logical network and the third logical network, the first logical network being in a first local access and transport area, the second logical network being an inter-exchange carrier network, the third logical network being in a second local access and transport area, and the first and second switches selected for polling based on the trap data indicating a problem at the first and second switches; and

identifying a failure of the logical circuit without manual intervention based on the polling.

11. The apparatus of claim 10, wherein the memory and the processor are located in a network management module separate from the switches forming the logical circuit.

12. The apparatus of claim 10, wherein the processor is to poll the first and second switches by periodically requesting second trap data from the first and second switches.

13. The apparatus of claim 12, wherein the processor is to identify the failure of the logical circuit by:

when the second trap data indicates that the first network-to-network interface is no longer communicating data, determining that the first network-to-network interface has failed;

after determining that the first network-to-network interface has failed, waiting a predetermined time period to determine whether the first network-to-network interface is restored; and

when after the predetermined time period, the first network-to-network interface is not restored, indicating that the logical circuit has failed.

14. The apparatus of claim 10, wherein the processor is to:

identify a logical identifier for the logical circuit; and

based on the logical identifier, access a database to identify a first logical connection associated with the first network-to-network interface and a second logical connection associated with the second network-to-network interface.

15. The apparatus of claim 14, wherein the logical identifier is a data link connection identifier (DLCI) or a virtual path/virtual circuit identifier (VPI/VCI).

16. A machine accessible storage device comprising instructions that, when executed, cause a machine to execute a method comprising:

analyzing non-requested trap data received from a plurality of switches forming a logical circuit, the logical circuit spanning first, second, and third logical networks;

polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit, the first switch forming a first network-to-network interface between the first logical network and the second logical network, the second switch forming a second network-to-network interface between the second logical network and the third logical network, the first logical network being in a first local access and transport area, the second logical network being an inter-exchange carrier network, the third logical network being in a second local access and transport area, and the first and second switches selected for polling based on the trap data indicating a problem at the first and second switches; and

identifying a failure of the logical circuit without manual intervention based on the polling.

17. The machine accessible storage device of claim 16, wherein polling the first and second switches comprises performing the polling via a network management module separate from the switches forming the logical circuit.

18. The machine accessible storage device of claim 16, wherein polling the first and second switches comprises periodically requesting second trap data from the first and second switches.

19. The machine accessible storage device of claim 16, wherein identifying the failure of the logical circuit comprises:

when the second trap data indicates that the at least one of the first or second network-to-network interfaces is no longer communicating data, then determining that the at least one of the first or second network-to-network interfaces has failed;

after determining that the at least one of the first or second network-to-network interfaces has failed, waiting a predetermined time period to determine whether the at least one of the first or second network-to-network interfaces is restored; and

when after the predetermined time period, the at least one of the first or second network-to-network interfaces is not restored, indicating that the logical circuit has failed.

20. The machine accessible storage device of claim 16, wherein the instructions are further to cause the machine to initiate a reroute procedure to reroute data from the logical circuit to a failover circuit in response to identifying the failure of the logical circuit to bypass the first and second network-to-network interfaces and the second logical circuit.