Powerline communication receiver

• US 8,711,995 B2
• Filed: 12/22/2011
• Issued: 04/29/2014
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Landis and Gyr Technologies LLC (Landis+Gyr Group AG)
• Original Assignee: Landis and Gyr Technologies LLC (Landis+Gyr Group AG)
• Inventors: Glende, James Hilmer
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US13/334,538
• Publication Number:
  US 20130163682A1
• Time in Patent Office: 859 Days
• Field of Search: 375/257, 375/355, 375/360
• US Class Current: 375/360
• CPC Class Codes: H04B 2203/5412 by modofying wave form of the power source
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04B 3/544 Setting up communications; Call and signalling arrangements
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/007 detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines. For a quadrature encoded signal, the input signal is separated into intermediary signals representing a real portion of and an imaginary portion. The processing circuit can then determine timing information from the real portion of and the imaginary portion. The intermediary signals can then be decimated according to a variable rate of decimation that is responsive to the determined timing information. The decimated intermediary signals are also filtered.

Claims

1. A circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC), the apparatus comprising:

a processing circuit configured and arranged to

receive an input signal representing the data communications over power distribution lines;

produce intermediary signals from each of a real portion of an input signal and an imaginary portion of the input signal;

detect symbol boundaries by processing the intermediary signals at an initial sample rate;

reduce the initial sample rate of the intermediary signals according to a decimation rate;

filter the intermediary signals at the reduced sample rate;

determine a timing mismatch between the detected symbol boundaries and samples corresponding to the reduced sample rate; and

adjust the decimation rate in response to the determined timing mismatch.

2. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to detect symbol boundaries by monitoring the input signal at the initial sample rate and detecting signal power peaks occurring between samples corresponding to the reduced sample rate.

3. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to determine the timing mismatch using the number of samples, at the initial sample rate, between a detected symbol boundary and a next sample corresponding to the reduced sample rate.

4. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to use the filtered intermediary signals to decode phase-encoded symbols carried by the intermediary signals.

5. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to provide delta phase discrimination and symbol decoding of the filtered intermediary signals.

6. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to filter the intermediary signals having the reduced sample rate using a comb filter that includes a feedback component that is responsive to the decimation rate.

7. The apparatus of claim 1, wherein the processing circuit is further configured and arranged to determine a timing mismatch for a set of synchronization symbols by ignoring timing data for a first two synchronization symbols of the set of synchronization symbols.

8. A circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC), the apparatus comprising:

a processing circuit configured and arranged to

receive an input signal representing the data communications over power distribution lines;

produce intermediary signals from each of a real portion of an input signal and an imaginary portion of the input signal;

process the intermediary signals to determine timing information for the intermediary signals;

decimate the intermediary signals according to a variable rate of decimation that is responsive to the determined timing information; and

apply a filter to the decimated intermediary signals.

9. The apparatus of claim 8, wherein the processing circuit is further configured and arranged to process the intermediary signals to determine timing information for the intermediary signals by detecting symbol boundaries.

10. The apparatus of claim 8, wherein the processing circuit is further configured and arranged to demodulate the intermediary signals according to one of quadrature phase shift keying (QPSK), differential phase shift keying (DPSK) and frequency shift keying (FSK).

11. A circuit-based method for receiving data communications over power distribution lines that carry power using alternating current (AC), the method comprising:

using a processing circuit to

receive an input signal representing the data communications over power distribution lines;

produce intermediary signals from each of a real portion of an input signal and an imaginary portion of the input signal;

detect symbol boundaries by processing the intermediary signals at an initial sample rate;

reduce the initial sample rate of the intermediary signals according to a decimation rate;

filter the intermediary signals at the reduced sample rate;

determine a timing mismatch between the detected symbol boundaries and samples corresponding to the reduced sample rate; and

adjust the decimation rate in response to the determined timing mismatch.

12. The method of claim 11, further including using the processing circuit to detect symbol boundaries by monitoring the input signal at the initial sample rate and detecting signal power peaks occurring between samples corresponding to the reduced sample rate.

13. The method of claim 11, further including using the processing circuit to determine the timing mismatch using the number of samples, at the initial sample rate, between a detected symbol boundary and a next sample corresponding to the reduced sample rate.

14. The method of claim 11, further including using the processing circuit to use the filtered intermediary signals to decode phase-encoded symbols carried by the intermediary signals.

15. The method of claim 11, further including using the processing circuit to provide delta phase discrimination and symbol decoding of the filtered intermediary signals.

16. The method of claim 11, further including using the processing circuit to filter the intermediary signals having the reduced sample rate using a comb filter that includes a feedback component that is responsive to the decimation rate.

17. The method of claim 11, further including using the processing circuit to determine a timing mismatch for a set of synchronization symbols by ignoring timing data for a first two synchronization symbols of the set of synchronization symbols.

18. The method of claim 11, further including using the processing circuit to perform the above steps for each of multiple channels that have different frequencies.

19. The method of claim 18, further including using the processing circuit to provide bandpass filtering for the multiple channels and frequencies.

20. A device comprising:

one or more processing circuits configured and arranged to include or provide

a first integrator configured to generate a first integration output representing the integration of a real portion of a symbol;

a second integrator configured to generate a second integration output representing the integration of an imaginary portion of the symbol;

a signal strength indicator configured to determine a signal strength from the first integration output and the second integration output;

a decimator controller configured to generate a decimator control signal in response the signal strength;

a first decimator configured to reduce a first sample rate of the first integration output to a sample rate that is controlled by the decimator control signal;

a second decimator configured to reduce a second sample rate of the second integration output to a sample rate that is controlled by the decimator control signal;

a first comb filter configured to filter the output of the first decimator; and

a second comb filter configured to filter the output of the second integrator.