Delta-sigma AD converter circuit and battery pack

• US 8,712,709 B2
• Filed: 01/12/2010
• Issued: 04/29/2014
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Mitsumi Electric Co., Ltd. (Minebea Mitsumi, Inc.)
• Original Assignee: Mitsumi Electric Co., Ltd. (Minebea Mitsumi, Inc.)
• Inventors: Abe, Makio
• Primary Examiner(s): Kundu, Sujoy
• Assistant Examiner(s): FORTICH, ALVARO E
• Application Number:
  US13/144,117
• Publication Number:
  US 20110270552A1
• Time in Patent Office: 1,568 Days
• Field of Search: 702/63
• US Class Current: 702/63
• CPC Class Codes: G01R 19/2509 Details concerning sampling, digitizing or waveform capturing
• CPC Class Codes: G01R 31/3842 combining voltage and current measurements
• CPC Class Codes: H03M 3/474 using time-division multiplexing
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A delta-sigma AD converter circuit includes a plurality of registers to store plural data obtained by dividing data stored in the shift register and to hold the plural data in such a form that each of the plural data is readable independently of the others, wherein one or more of the plurality of registers store the pulse density modulated data stored in the shift register in response to the register store instruction signal, and the filtering unit reads the pulse density modulated data from one or more of the plurality of registers responsive to the mode in response to the read request signal.

Claims

1. A delta-sigma AD converter circuit, comprising:

a modulation unit to produce pulse density modulated data by pulse density modulation of an analog signal; and

a filtering unit to convert the pulse density modulated data into pulse code modulated data,

wherein the modulation unit includes;

a shift register to store and shift the pulse density modulated data in synchronization with a clock, said shift register having a bit width;

a counter to generate a register store instruction signal and a read request signal upon a count value reaching a predetermined value responsive to a mode, the count value being a count of a number of shifts of the shift register; and

a plurality of conversion result registers to store plural data obtained by dividing data stored in the shift register and to hold the plural data in such a form that each of the plural data is readable independently of the others,

wherein each register comprising said plurality of conversion result registers has a bit width that is less than the bit width of said shift register,

wherein each register comprising said plurality of conversion result registers stores a portion of the pulse density modulated data stored in the shift register in response to the register store instruction signal, and the filtering unit reads the pulse density modulated data from one or more of the plurality of conversion result registers according to the mode, in response to the read request signal.

2. The delta-sigma AD converter circuit as claimed in claim 1, wherein the mode is set by the filtering unit.

3. The delta-sigma AD converter circuit as claimed in claim 1, wherein the modulation unit includes a reset circuit that resets, according to a setting made by the filtering unit, a conversion start signal requesting an operation of the counter upon receiving the read request signal from the counter.

4. The delta-sigma AD converter circuit as claimed in claim 1, wherein the filtering unit reads the pulse density modulated data of a first bit width in a case of the mode being a first mode, and reads the pulse density modulated data of a second bit width different from the first bit width in a case of the mode being a second mode.

5. The delta-sigma AD converter circuit as claimed in claim 1, wherein one or more of the plurality of conversion result registers store the pulse density modulated data of a first bit width in a case of the mode being a first mode, and store the pulse density modulated data of a second bit width different from the first bit width in a case of the mode being a second mode.

6. The delta-sigma AD converter circuit as claimed in claim 1, wherein the filtering unit is a CPU.

7. A battery pack, comprising:

a battery;

a current sensor to detect charge and discharge currents of the battery;

a delta-sigma modulator to produce pulse density modulated data by pulse modulation of an analog signal generated by the current sensor; and

a CPU to obtain digital values of the charge and discharge currents based on the pulse density modulated data,

wherein the delta-sigma modulator includes;

a shift register to store and shift the pulse density modulated data in synchronization with a clock, said shift register having a bit width;

a counter to generate a register store instruction signal and a read request signal upon a count value reaching a predetermined value responsive to a mode, the count value being a count of a number of shifts of the shift register; and

a plurality of conversion result registers to store plural data obtained by dividing data stored in the shift register and to hold the plural data in such a form that each of the plural data is readable independently of the others,

wherein each register comprising said plurality of conversion result registers has a bit width that is less than the bit width of said shift register,

wherein each register comprising said plurality of conversion result registers stores a portion of the pulse density modulated data stored in the shift register in response to the register store instruction signal, and wherein the CPU reads the pulse density modulated data from one or more of the plurality of conversion result registers according to the mode, in response to the read request signal, and calculates a remaining battery level of the battery based on the digital values of the charge and discharge currents obtained based on the read pulse density modulated data.

8. The battery pack as claimed in claim 7, wherein the mode is set by the CPU.

9. The battery pack as claimed in claim 7, wherein the delta-sigma modulator includes a reset circuit that resets, according to a setting made by the CPU, a conversion start signal requesting an operation of the counter upon receiving the read request signal from the counter.

10. The battery pack as claimed in claim 7, wherein the CPU reads the pulse density modulated data of a first bit width in a case of the mode being a first mode, and reads the pulse density modulated data of a second bit width different from the first bit width in a case of the mode being a second mode.

11. The battery pack as claimed in claim 7, wherein one or more of the plurality of conversion result registers store the pulse density modulated data of a first bit width in a case of the mode being a first mode, and store the pulse density modulated data of a second bit width different from the first bit width in a case of the mode being a second mode.