Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders

• US 8,713,081 B2
• Filed: 04/18/2013
• Issued: 04/29/2014
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US13/865,891
• Publication Number:
  US 20130311534A1
• Time in Patent Office: 376 Days
• Field of Search: 708/235, 708/300, 708/493
• US Class Current: 708/235
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 7/5057 using table look-up; using programmable logic arrays G06F7/509 takes precedence
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: G06F 7/509 for multiple operands, e.g. digital integrators

Abstract

A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Claims

1. A device, comprising:

a plurality of logic modules including a first logic module and a second logic module, the first logic module configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit, the second logic module configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit;

logic circuitry configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the quaternary addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

2. The device of claim 1, wherein the first logic module is configured to receive the first sum bit, the fourth input bit, and a previous rank first carry bit to generate a second carry bit.

3. The device of claim 2, wherein the logic circuitry includes XOR circuitry configured to receive the first sum bit, the fourth input bit, and a previous rank first carry bit for combination with a previous rank second carry bit to generate the result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

4. The device of claim 2, wherein the first logic module and the second logic module reside in an adaptive logic module.

5. The device of claim 1, further comprising a multiplexer configured to receive the fourth input bit and a previous rank first carry bit to select a second carry bit.

6. The device of claim 5, wherein XOR circuitry comprises two XOR gates, the first XOR gate configured to receive the fourth input bit and the first sum bit to generate a selection bit to control the multiplexer.

7. The device of claim 6, wherein the second XOR gate is configured to receive the previous rank first carry bit and the selection bit to generate a second sum bit.

8. The device of claim 7, wherein the second sum bit is added with the previous rank second carry bit to generate the result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

9. The device of claim 8, wherein the second sum bit is combined with the previous rank second carry bit and a previous rank ripple carry bit to generate a ripple carry bit.

10. The device of claim 1, wherein device is a programmable chip.

11. A logic circuitry including a quaternary adder, the logic circuitry comprising:

a first logic circuitry configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit;

a second logic circuitry configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit in the same clock cycle the first carry bit is output; and

a third logic circuitry configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

12. The logic circuitry of claim 11, further comprising a third logic circuitry configured to receive the first sum bit, the fourth input bit, and a previous rank first carry bit to generate a second carry bit.

13. The logic circuitry of claim 12, wherein the third logic circuitry includes XOR circuitry configured to receive the first sum bit, the fourth input bit, and a previous rank first carry bit for combination with a previous rank second carry bit to generate the result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

14. The logic circuitry of claim 12, wherein the first logic circuitry, the second logic circuitry, and the third logic circuitry reside on the same level of logic.

15. The logic circuitry of claim 11, further comprising a multiplexer configured to receive the fourth input bit and a previous rank first carry bit to select a second carry bit.

16. The logic circuitry of claim 15, wherein XOR circuitry comprises two XOR gates, the first XOR gate configured to receive the fourth input bit and the first sum bit to generate a selection bit to control the multiplexer.

17. The logic circuitry of claim 16, wherein the second XOR gate is configured to receive the previous rank first carry bit and the selection bit to generate a second sum bit.

18. The logic circuitry of claim 17, wherein the second sum bit is combined with the previous rank second carry bit to generate the result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

19. The logic circuitry of claim 18, wherein the second sum bit is combined with the previous ranking second carry bit and a previous rank ripple carry bit to generate a ripple carry bit.

20. The logic circuitry of claim 11, wherein logic circuitry is implemented using an adaptive logic module on a programmable chip.

21. A device, comprising:

first logic circuitry means configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit;

second logic circuitry means configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit in the same clock cycle the first carry bit is output;

third logic circuitry means configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.