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Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders

  • US 8,713,081 B2
  • Filed: 04/18/2013
  • Issued: 04/29/2014
  • Est. Priority Date: 03/25/2010
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a plurality of logic modules including a first logic module and a second logic module, the first logic module configured to receive a first input bit, a second input bit, and a third input bit and output a first carry bit, the second logic module configured to receive the first input bit, the second input bit, and the third input bit and output a first sum bit;

    logic circuitry configured to receive a fourth input bit and the first sum bit to allow generation of a result bit for the quaternary addition of the first input bit, the second input bit, the third input bit, and the fourth input bit.

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