Data scrambling in memory devices

• US 8,713,330 B1
• Filed: 10/28/2009
• Issued: 04/29/2014
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sommer, Naftali, Anholt, Micha, Golov, Oren, Perlmutter, Uri, Winter, Shai
• Primary Examiner(s): Hoffman, Brandon
• Assistant Examiner(s): Ambaye, Samuel
• Application Number:
  US12/607,078
• Time in Patent Office: 1,644 Days
• Field of Search: 713/193, 714/773, 714/168
• US Class Current: 713/193
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A method for data storage includes scrambling data for storage in a memory device using a given scrambling seed. A statistical distribution of the scrambled data is assessed, and a measure of randomness of the statistical distribution is computed. A scrambling configuration of the data is modified responsively to the measure of randomness, and the data having the modified scrambling configuration is stored in the memory device.

Claims

1. A method for data storage, comprising:

encoding data for storage in a memory device with an Error Correction Code (ECC);

encoding a given scrambling seed with the ECC;

scrambling the encoded data dependent upon the encoded scrambling seed;

determining a statistical distribution of the scrambled encoded data;

computing a measure of randomness of the scrambled encoded data dependent upon the determined statistical distribution; and

modifying a scrambling configuration of the scrambled encoded data dependent upon the computed measure of randomness;

storing the encoded data having the modified scrambling configuration in the memory device;

wherein scrambling the encoded data comprises;

encoding two or more candidate scrambling seeds with the ECC;

scrambling the encoded data with each of the two or more encoded candidate scrambling seeds, to create a respective two or more scrambled encoded data;

wherein computing the measure of randomness comprises computing a respective level of randomness for each of the respective two or more scrambled encoded data; and

wherein modifying the scrambling configuration comprises selecting one of the respective two or more scrambled encoded data dependent upon the respective levels of randomness.

2. The method according to claim 1, wherein computing the measure of the randomness comprises comparing a first number of “

0”

bit values in the scrambled encoded data with a second number of “

1”

bit values in the scrambled data.

3. The method according to claim 1, wherein modifying the scrambling configuration comprises adding one or more dummy bits to the scrambled encoded data.

4. The method according to claim 1, wherein modifying the scrambling configuration comprises;

encoding another scrambling seed with the ECC, wherein the another scrambling seed is different than the given scrambling seed;

scrambling the encoded data using another scrambling seed, dependent upon the encoded another scrambling seed.

5. The method according to claim 1, wherein scrambling the encoded data comprises operating two or more scrambling units concurrently, each scrambling unit scrambling the encoded data using a respective one of the two or more encoded candidate scrambling seeds.

6. The method according to claim 1, wherein modifying the scrambling configuration comprises dividing the encoded data into multiple sections, scrambling the encoded data in at least one of the sections using one of the two or more encoded candidate scrambling seeds, and scrambling the encoded data in at least another of the sections using another of the two or more encoded candidate scrambling seeds.

7. The method according to claim 1, wherein modifying the scrambling configuration comprises dividing the encoded data into multiple sections, scrambling the encoded data in at least one of the sections using a scrambling sequence derived from the encoded scrambling seed, and scrambling the encoded data in at least another of the sections using an inverse of the scrambling sequence.

8. The method according to claim 1, wherein the memory device comprises a group of multi-level memory cells, each storing at least first and second bits in one of multiple different memory states, and wherein modifying the scrambling configuration comprises balancing respective numbers of the memory cells in the group that are programmed to the different programming states.

9. The method according to claim 8, wherein the first bits of the memory cells in the group store a first memory page and the second bits of the memory cells in the group store a second memory page, and wherein balancing the numbers comprises selecting first and second scrambling seeds, for respectively scrambling the first and second memory pages, from respective first and second disjoint sets of candidate scrambling seeds.

10. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory device; and

a processor, which is configured to;

encode data for storage in the memory device with an Error Correction Code (ECC);

encode a scrambling seed with the ECC;

scramble the encoded data for storage in the memory device dependent upon the encoded scrambling seed;

determine a statistical distribution of the scrambled encoded data;

compute a measure of randomness of the scrambled encoded data dependent upon the determined statistical distribution;

modify, a scrambling configuration of the scrambled encoded data dependent upon the computed measure of randomness of the scrambled data;

store the scrambled encoded data having the modified scrambling configuration in the memory device.

11. The apparatus according to claim 10, wherein to compute the measure of the randomness, the processor is further configured to compare a first number of “

0”

bit values in the scrambled encoded data with a second number of “

1”

bit values in the scrambled encoded data.

12. The apparatus according to claim 10, wherein to modify the scrambling configuration, the processor is further configured to add one or more dummy bits to the scrambled encoded data.

13. The apparatus according to claim 10, wherein to modify the scrambling configuration, the processor is further configured to encode another scrambling seed, different from the given scrambling seed, and scramble the encoded data dependent upon the encoded another scrambling seed;

wherein encode the scrambling seed with the ECC, the processor is further configured to encode two or more candidate scrambling seeds with the ECC, and wherein to scramble the encoded data, the processor is further configured to;

scramble the encoded data with each of the two or more candidate scrambling seeds to create a respective two or more scrambled encoded data;

compute a respective level of randomness for each of the respective two or more scrambled encoded data; and

select one of the respective two or more scrambled encoded data scrambled dependent upon the respective levels of randomness.

14. The apparatus according to claim 10, wherein the processor comprises two or more scrambling units operating concurrently, each configured to scramble the encoded data using a respective one of the two or more encoded candidate scrambling seeds.

15. The apparatus according to claim 10, wherein to scramble the encoded data, the processor is further configured to divide the encoded data into multiple sections, to scramble the encoded data in at least one of the sections using one of the two or more encoded candidate scrambling seeds, and to scramble the encoded data in at least another of the sections using another of the two or more encoded candidate scrambling seeds.

16. The apparatus according to claim 10, wherein to scramble the encoded data the processor is further configured to divide the encoded data into multiple sections, to scramble the encoded data in at least one of the sections using a scrambling sequence derived from the encoded scrambling seed, and to scramble the encoded data in at least another of the sections using an inverse of the scrambling sequence.

17. The apparatus according to claim 10, wherein the memory device comprises a group of multi-level memory cells, each storing at least first and second bits in one of multiple different memory states, and wherein the processor is further configured to balance respective numbers of the memory cells in the group that are programmed to the different programming states.

18. The apparatus according to claim 17, wherein the processor is further configured to store a first memory page in the first bits of the memory cells in the group, and a second memory page in the second bits of the memory cells in the group, and to balance the numbers by selecting first and second scrambling seeds, for respectively scrambling the first and second memory pages, from respective first and second disjoint sets of candidate scrambling seeds.

19. A computer-accessible non-transitory storage medium having program instructions stored therein that, in response to execution by a computer system, cause the computer system to perform operations including:

receiving, from a host, data to be stored in a memory device;

encoding the received data with an Error Correction Code (ECC);

initializing a scrambling seed;

encoding the scrambling seed with the ECC;

scrambling the encoded data dependent upon the encoded scrambling seed;

determining a statistical distribution of the scrambled encoded data;

computing a measure of randomness of the scrambled encoded data dependent upon the statistical distribution;

modifying the encoded scrambling seed dependent upon the computed measure of randomness;

re-scrambling the encoded data dependent upon the modified encoded scrambling seed; and

storing the re-scrambled encoded data into the memory device;

wherein scrambling the encoded data comprises;

encoding two or more candidate scrambling seeds with the ECC;

scrambling the encoded data with each of the two or more encoded candidate scrambling seeds, to create a respective two or more scrambled encoded data;

wherein computing the measure of randomness comprises computing a respective level of randomness for each of the respective two or more scrambled encoded data; and

wherein modifying the scrambling configuration comprises selecting one of the respective two or more scrambled encoded data dependent upon the respective levels of randomness.

20. The computer-accessible non-transitory storage medium of claim 19, wherein computing the measure of randomness comprises determining a number of “

0”

bit values and a number of “

1”

bit values in the scrambled encoded data.

21. The computer-accessible non-transitory storage medium of claim 20, wherein computing the measure of randomness further comprises comparing the difference between the number of “

0”

bit values and the number “

1”

bit values, and a pre-determined threshold value.

22. The computer-accessible non-transitory storage medium of claim 19, wherein modifying the scrambling seed comprises dividing the encoded data into multiple sections, scrambling the encoded data in at least one of the sections using a scrambling sequence derived from the scrambling seed, and scrambling the encoded data in at least another of the sections using an inverse of the scrambling sequence.