Apparatus and method for layered decoding in a communication system using low-density parity-check codes

• US 8,713,397 B2
• Filed: 05/11/2011
• Issued: 04/29/2014
• Est. Priority Date: 05/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Hyun-Koo, Jeong, Hong-Sil, Myung, Se-Ho, Kim, Jae-Yoel
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US13/105,527
• Publication Number:
  US 20110283158A1
• Time in Patent Office: 1,084 Days
• Field of Search: 714/752
• US Class Current: 714/752
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/114 Shuffled, staggered, layered or turbo decoding schedules
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/1168 wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
• CPC Class Codes: H03M 13/1177 Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders.

Claims

1. A channel decoding method comprising the steps of:

extracting a parity-check matrix;

grouping rows of the parity-check matrix into one or more groups;

grouping rows of each group into one or more sub-groups, if the each group has two or more non-zero elements in a column direction; and

determining input and/or output orders for each row of the one or more sub-groups,

wherein each row of the one or more sub-groups is processed in parallel.

2. The channel decoding method of claim 1, wherein grouping rows comprises:

grouping rows of the parity-check matrix to avoid overlapping input and/or output values in the column direction between rows of each group.

3. The channel decoding method of claim 1, wherein determining comprises:

determining at least one of the input orders and the output orders of the grouped rows to avoid overlapping input and/or output values in the column direction between layers of each group.

4. The channel decoding method of claim 1, wherein, when a Quasi-Cyclic Low-Density Parity-Check (QC-LDDC) code is layer-decoded, input and/or output values are not overlapped in the column direction between adjacent layers in the parity check matrix, wherein the QC-LDPC has one block being a sum of two or more permutation matrices.

5. A channel decoding apparatus comprising:

an extractor for extracting a parity-check matrix; and

a controller for grouping rows of the parity-check matrix into one or more groups, grouping rows of each group into one or more sub-groups, if the each group has two or more non-zero elements in a column direction, and determining input and/or output orders for each row of the one or more sub-groups,

wherein each row of the one or more sub-groups is processed in parallel.

6. The channel decoding apparatus of claim 5, wherein the controller groups the rows of the parity-check matrix so that input and/or output values are not overlapped in the column direction between rows of each group.

7. The channel decoding apparatus of claim 5, wherein at least one of the input orders and the output orders of the grouped rows are determined so that input and/or output values are not overlapped in the column direction between layers of each group.

8. The channel decoding apparatus of claim 5, wherein when a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code is layered-decoded, input and/or output values are not overlapped in the column direction between adjacent layers in the parity check matrix, wherein the QC-LDPC has one block being a sum of two or more permutation matrices.