Controller interface providing improved data reliability

• US 8,713,404 B2
• Filed: 07/01/2011
• Issued: 04/29/2014
• Est. Priority Date: 07/01/2011
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fai, Anthony, Seroff, Nicholas, Wakrat, Nir Jacob
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US13/175,610
• Publication Number:
  US 20130007562A1
• Time in Patent Office: 1,033 Days
• Field of Search: 714/763, 714/718, 714/721, 714/748, 714/758, 714/768, 714/799, 714/6.1, 714/30, 714/42, 714/48, 324/314, 324/500, 365/201, 365/185.09, 365/185.03, 365/185.33, 365/185.24
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Claims

1. A memory device comprising:

non-volatile memory;

a memory controller communicatively coupled to the non-volatile memory over a first bus;

a host interface through which the memory controller communicates with a host device over a second bus; and

a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

2. The memory device of claim 1, wherein signal level data includes one or more center-point voltages that indicate one or more center-points between voltage ranges used by the host device to represent data values.

3. The memory device of claim 2, wherein the one or more center-point voltages include one center-point voltage indicating a center point between binary data values transmitted by the host device.

4. The memory device of claim 2, wherein the one or more center-point voltages include multiple center-point voltages indicating multiple center points between multi-level data values transmitted by the host device.

5. The memory device of claim 2, wherein the signal conditioner adjusts the signals received over the second bus based on a difference between the one or more center-point voltages provided by the host device and one or more center-point voltages used by the memory device.

6. The memory device of claim 1, further comprising a reference voltage pin of the host interface that is configured to provide the signal level data from the host device.

7. The memory device of claim 1, further comprising an error correction circuit of the host interface that, using the conditioned signals from the signal conditioner, corrects errors associated with data chunks transmitted over the second bus based on one or more bits of metadata transmitted with the data chunks.

8. The memory device of claim 7, wherein the error correction circuit includes a cyclic redundancy check (CRC) circuit.

9. The memory device of claim 8, wherein the metadata includes a check value that is generated by the host device for each of the data chunks using a CRC encoding algorithm.

10. The memory device of claim 7, wherein, when an uncorrectable error is detected in a particular data chunk, the error correction circuit transmits a request for retransmission of the particular data chunk.

11. The memory device of claim 7, wherein, when a number of errors detected by the error correction circuit over a particular time period exceed a threshold number, the error correction circuit instructs the host device to reduce a data transmission speed associated with the second bus.

12. The memory device of claim 7, wherein, when a number of errors detected by the error correction circuit over a particular time period are less than a threshold number, the error correction circuit instructs the host device to increase a data transmission speed associated with the second bus.

13. A system comprising:

a host device that includes a host controller; and

one or more non-volatile memory packages that are each communicatively coupled to the host device over one or more communication channels, wherein the host controller of the host device provides one or more commands to the non-volatile memory packages over the one or more communication channels, wherein each of the non-volatile memory packages includes;

non-volatile memory;

a memory controller that is communicatively coupled to the non-volatile memory;

a host interface through which the memory controller communicates with a host device over the one or more communication channels; and

a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the one or more communication channels based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the one or more communication channels.

14. The system of claim 13, wherein signal level data includes one or more center-point voltages that indicate one or more center-points between voltage ranges used by the host device to represent data values.

15. The system of claim 14, wherein the one or more center-point voltages include one center-point voltage indicating a center point between binary data values transmitted by the host device.

16. The system of claim 14, wherein the one or more center-point voltages include multiple center-point voltages indicating multiple center points between multi-level data values transmitted by the host device.

17. The system of claim 14, wherein the signal conditioner adjusts the signals received over the one or more communication channels based on a difference between the one or more center-point voltages provided by the host device and one or more center-point voltages used by the memory device.

18. The system of claim 13, further comprising a reference voltage pin of the host interface that is configured to provide the signal level data from the host device.

19. The system of claim 13, wherein each of the non-volatile memory packages further include:

an error correction circuit of the host interface that, using the conditioned signals from the signal conditioner, corrects errors associated with data chunks transmitted over the one or more communication channels based on one or more bits of metadata transmitted with the data chunks.

20. The system of claim 19, wherein the error correction circuit includes a CRC circuit.

21. The system of claim 20, wherein the metadata includes a check value that is generated by the host device for each of the data chunks using a CRC encoding algorithm.

22. The system of claim 19, wherein, when an uncorrectable error is detected in a particular data chunk, the error correction circuit transmits a request for retransmission of the particular data chunk.

23. The system of claim 19, wherein, when a number of errors detected by the error correction circuit over a particular time period exceed a threshold number, the error correction circuit instructs the host device to reduce a data transmission speed associated with the one or more communication channels.

24. The system of claim 19, wherein, when a number of errors detected by the error correction circuit over a particular time period are less than a threshold number, the error correction circuit instructs the host device to increase a data transmission speed associated with the one or more communication channels.

25. A method comprising:

receiving, at an interface of a memory device, signals transmitted by a host device to the memory device over a bus;

receiving, at the interface of the memory device, signal level data from the host device that relates to one or more voltage levels of signals generated by the host device to encode data transmitted across the bus; and

conditioning, by the interface, the received signals based on the received signal level data from the host device.

26. The method of claim 25, wherein the received signal is conditioned by a signal conditioner that is part of the interface of the memory device.

27. The method of claim 25, wherein signal level data includes one or more center-point voltages that indicate one or more center-points between voltage ranges used by the host device to represent data values.

28. The method of claim 27, wherein the signals are conditioned based on a difference between the one or more center-point voltages provided by the host device and one or more center-point voltages used by the memory device.

29. The method of claim 25, further comprising correcting, by the interface and using the conditioned signals, errors associated with data chunks transmitted over the bus based on one or more bits of metadata transmitted with the data chunks.

30. The method of claim 29, wherein errors associated with the data chunks are conditioned by an error correction circuit that is part of the interface of the memory device.

31. The method of claim 29, wherein the errors are corrected with a CRC algorithm using check values that are generated by the host device for each of the data chunks and that are included in the metadata.

32. The method of claim 29, further comprising transmitting a request to the host device for retransmission of a particular data chunk in response to detecting an error associated with the particular data chunk that is uncorrectable.

33. The method of claim 29, further comprising instructing the host device to reduce a data transmission speed associated with the bus in response to detecting greater than a threshold number of errors in data transmitted by the received signals over a time period.

34. The method of claim 29, further comprising instructing the host device to increase a data transmission speed associated with the bus in response to detecting less than a threshold number of errors in data transmitted by the received signals over a time period.